The program xcircuit is a generic drawing program tailored especially
for making publication-quality renderings of circuit diagrams (hence
the name). The output is pure PostScript, and the graphical interface
attempts to maintain as much consistency as possible between the X11
window rendering and the final printer output.
xcircuit is mouse, menu, and keyboard-driven, with the emphasis on
single-character keyboard macros.
Package provided by Jason Beegan <jasontd@indigo.ie> in PR 11383 with
some minor modifications by me.
from the authors announcement:
-----------------------------
The loadable target module API is starting to take shape.
That is the major thrust nowadays with Icarus Verilog, after all, so
progress is being made here. The biggest change is in fact a philosophy
change. The target module now needs only a single symbol -- target_design --
to receive the whole design. The target module can from there and using
the API access the entire design randomly. So if you wanted to implement
a graphical browser, you could:-)
I've added support for the l-values of procedural assignments, and also
back pointers to objects that reference ivl_nexus_t objects. This closes
the loop so that there should be no dead-ends in the design.
I've clarified and expanded the descriptions in the ivl_target.h header
file. There should be just about enough documentation to properly used
all the various types. (Have any of you tried to write GIMP plug-ins?
Have you looked at the libgimp header files? Have you seen any comments
there?-( I won't ever sink to that level, I hope.)
I've also imtegrated updates to the Cygwin32 port to support loadable
targets under Cygwin32. After much struggling, Venkat managed to discover
the secret magic needed to get load time symbol binding to work. Hopefully
I didn't break it too bad when I changed the API again. (I think it is
still fine.)
as files instead of requiring the user to install one of our largest packages
just to build them. Note, in the previous version of this pkg, the docs generated
with latex weren't even being installed (!).
Notable changes since the last pkged version are:
Gwave NEWS --- history of user-visible changes. -*- text -*-
New in 20000518:
- Logarithmic scales working on both X and Y axis.
New in 20000509:
- First public guile/guile-gtk release.
- Popup menu on visible-wave button can activate per-waveform dialog box
- Logarithmic scale on Y axis working; on X axis it isn't quite there yet.
New in 20000108:
- Merged in guile and guile-gtk; the GUI is mostly written in guile now.
- Some additional improvements to reading of HSPICE input. Reading partial
files from simulations still in progress works for ascii .tr0 files.
Changes included in version 2.0.4
---------------------------------
- Fixed printing under windows.
- You can now plot the real and imaginary parts of the
circuit input and output impedances
Changes included in version 2.0.3
---------------------------------
- Moved to Qt version 2.1.0
- The help browser is now integrated into the ViPEC application.
- Fixed a bug in calculating the circuit output impedance.
- Input and output impedances ouput to a graph now works.
Changes included in version 2.0.2
---------------------------------
- Improved data storage of graphs and Smith charts
- Double buffering implemented for drawing of graphs
and Smith charts to reduce flicker.
- Improved font management
- Fixed display bug in Table view
- Fixed bug with output to 2 port parameter files under Windows
- Added support for Group Delay, see help files for more details
as well as sample circuit: group_delay.ckt
ACS 0.27 release notes (06/03/2000)
New features:
1. BSIM3 model, DC.
They work for AC and transient analysis, but only the DC effects
actually work. The next release should have the charge effects. For
now, it fakes it with Meyer's model.
2. A first cut at a model compiler, to aid in development of new
models. Models are described in a ".model" file, which is processed
to automatically generate the ".h" and ".cc" files. This version
fully handles the ".model" statement part of it, but leaves the device
and common sections the old way. Eventually, the entire process will
be automated. The old way still works.
3. "Fit" behavioral modeling function, which fits a curve to a set of
data. You can specify the order of the fit, which is piecewise
polynomials. For now, the order may be 1 (linear, like PWL) or 3
(cubic splines). You may also specify the boundary consitions.
4. More probes.
Some things that are partially implemented:
1. Internal element: non-quasi-static poly-capacitor. It is needed by
the BSIM3 and EKV models. Eventually, it will be available as a
netlist item, but not yet.
Bug fixes:
1. PWL could fail if there were duplicate points at the beginning. It
still does, but gives a reasonable error message.
2. Some "dot commands" were ignored if there were spaces before the
dot. This was particularly annoying if the line was supposed to be
".end" which should make it exit. It didn't, leaving it in
interactive mode, a major annoyance in a script.
Other improvements:
1. There is a change to the way integration in capacitors is done. It
is now strictly based on charge (i = dq/dt). The old version was
based on capacitance (i = C * dv/dt) which is strictly incorrect. The
dC/dt term was missing (i = C * dv/dt + v * dC/dt). This is a
non-issue when C is constant.
2. More documentation on internals.
Changes that I think are improvements, but some may disagree:
1. The command line is a little different. In the old version,
"acs file" would run it, and whether it exited or not depended on
whether there was an ".end" line. Now, by default, it just loads the
file in preparation for interactive use. If you want batch mode, say
"acs -b file".
2. The regression suite is included in the standard distribution.
Changes that are not really improvements:
1. Due to the model compiler, the build process is a little more
complicated. To do a complete build, you must build the model
compiler first, then the simulator. If you are not making any new
models, you can probably get away with just building the simulator.
This will change in a future release.
Bugs:
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. The makefile does not set up the proper link for the model
compiler. You need to do it manually.
Hot items for a future release (no promises, but highly probable):
1. Charge effects in BSIM models. They are computed, but not loaded
to the matrix.
2. Completion of model compiler, and its documentation.
3. Completion of multi-rate.
4. Homotopy methods to improve convergence.
5. Transmission line accuracy and speed improvements, using a step
control mechanism similar to that used for capacitors.
6. Parameterized subcircuits and defined parameters.
7. A "trigger" element, so time dependent values can be triggered by
the circuit, as an alternate to simple time.
To reach me, try this email address:
aldavis@ieee.org
ACS ftp sites:
ftp://ftp.geda.seul.org/pub/geda/dist/acs-0.27.tar.gz
http://www.geda.seul.org/dist/acs-0.27.tar.gz
ftp://sunsite.unc.edu/pub/Linux/apps/circuits/acs-0.27.tar.gz
are (from the authors announcements):
--------------------------------
Icarus Verilog snapshot 20000721
--------------------------------
(first snapshot after the 0.3 release)
This snapshot adds no new features or language support, but is working
towards more precise interpretation of scheduling and value propagation
details.
The first thing I've done is redesign the internal Link structure that
is used to connect the internal netlist together. There are some aspects
of the nexos of a set of links that were carried by the Link class or
by external functions. These have been moved to the new Nexus class and
linking and structure has improved because of it.
This has led me to modify the handing of signal initial values. In practice,
the time-0 value of a net is a property of the nexus instead of the objects
that are connected together, so I have implemented it so, and in the
process fixed a bunch of initial value problems.
One new feature that is added is support for non-constant delay expressions.
Now, you can even have something like ``#($random%256) <statement>'' and
expect it to do what you think. (So now the telephone example in James
Lee's "Verilog Qickstart" actually works!)
I've added some missing support for various operators in constant expressions.
I've also added some more of the friends of $random for those folks who
do stochastic modeling.
Constant propagation carries some new bug fixes, and some new smarts. It
is for example able to detect a mux with a constant 'bz input and replace
it with bufif devices, and other clevernesses with logic reduction.
--------------------------------
Icarus Verilog snapshot 20000729
--------------------------------
Like I said, the `timescale compiler directive now more or less works.
You can now specify timescale for modules, and the compiler will figure
out a global design resolution and scale your time values to match. The
VCD dumps should reflect the chosen resolution automatically. Floating
point notation is not yet supported, we'll see if that turns out to be
a problem.
A problem with `timescale support is that the compiler will allow unitless
modules. This can happen if you have `timescale late in the source file.
The default unit is the not-very-intuitive 1s. Frankly, I don't like the
`timescale semantics for this sort of reason, but its an accepted
standard, so I'm stuck with it.
I've also added support for min:typ:max expressions. The compiler chooses
one of the three expressions at compile time, based on a compile time
switch. You can ask for min typ or max values via the "-Tmin" etc. switch
to the iverilog command. If you do not specify a switch, the compiler will
choose the typ values but print warnings. The -Ttyp switch will suppress
the warnings.
I have fixed yet more net initialization bugs. These are getting pretty
subtle, now, so you should have a hard time tickling any remaining errors
here. I've also fixed a nasty and subtle bug in event expression support.
This bug only happened when the design had many event expressions with
many conjunctions.
Although they are not ready for use, I have made some forward progress
with disable statements. I now at least elaborate them, so now I just need
to figure out how to make the run-time work out. That's the hard part,
I'm afraid.
--------------------------------
Icarus Verilog snapshot 20000805
--------------------------------
I've finally dealt with a problem that's been nagging at me for a while.
Until now, it has been possible that excessively clever hierarchical
references into and out of task scopes could confound symbol lookup.
I think I finally put that to rest, and in the process reorganized the
netlist format for holding task definitions. It should no longer be
possible to confuse name binding in Icarus Verilog.
Found and fixed a silly bug in elaborating e?a:'bz and e?'bz:a expressions
into bufifN devices. I got the sense of the enable wrong in one of the
cases. All fixed (and the test suite updated to catch this silly mistake:-)
tri0 and tri1 nets should now work properly. These are mostly a run-
time issue which I solved using resolution functions. This is actually
a technique that I borrowed from VHDL.
For those of you doing XNF synthesis, I fixed up my FF/RAM detector to
allow <= assignments in always blocks. This is in fact the preferred way
to describe DFFs as <= more accurately simulates their RTL nature.
Also found and fixed a few DOS \r\n line end issues in the lexical ana-
lyser and the preprocessor. We sometimes forget how tricky these line-
end problems can be, and compiler directives are the most susceptible.
This problem most likely occurs when you transport files from a DOS
environment. (The MAC folks haven't complained much, so either I got it
right for them, or Kato took care of the problems for me:-)
Changes since 9.0g are (from the NEWS file):
Changes in Dinotrace 9.0k 7/17/2000
Fixed bug with $comment after $enddefinitions. [Harunobu Miyashita]
Fixed Tempest reading signals over 128 bits. [Ta-Chung Chang]
This bug was introduced in 9.0i.
Fixed portability bug with Value Examine showing 0s. [Ta-Chung Chang]
Fixed Verilog reading with large time intervals. [Matthias Wenzel]
Changes in Dinotrace 9.0i 5/1/2000
Major speed improvement in reading Tempest traces.
All trace formats now have less processing when building busses from
individual bits. [Steve Hoover]
ASCII traces assume extra time so last line is not lost.
ASCII traces which had timestamps would not show the last state of the
bus, as Dinotrace did not guess at how long that last state was valid for.
Now, it looks at the smallest time step in the trace, and uses that
as a guess at the timescale. [Pani Kodandapani]
which takes entries of the format <make-definition-name>=<pkgname>. This
has not been added to MAKEFLAGS because (a) premature optimisation is the
root of all evil, and (b) because the .for loop used to implement this
shows the wrong results when multiple prefices are evaluated.
Modify all the package Makefiles to use EVAL_PREFIX, thereby simplifying
them considerably.
ALso simplify the logic to calculate the prefix as well.
package's prefix would not work as part of the environment specification
via MAKE_ENV (as it would not be executed in the correct directory).
Fix this by invoking pkg_info(1) directly, not via an intermediate make(1)
step - this is not as clean, but more effective (i.e. it works).
a bit more user-friendly.
Introduce a show-{gtk+,imlib,kdebase,qt1,qt2,xpm}-prefix target in
bsd.pkg.mk, and use "${MAKE} show-*-prefix" in package Makefiles.
Changes, from the authors release statement, are:
This release is a significant improvement over previous releases of
Icarus Verilog, including better language coverage, improved
synthesis, and increased performance.
This release adds to the 0.2 release support for Verilog-2000 style
parameters and parameter overrides, defparam, and localparam,
including proper handling of scoping rules. Also, strength modeling is
added, with support for strengths attached to gates and continuous
assignments.
Combinational user defined primitives have been added to complement
synchronous primitives that were already supported. Support for
primitives should now be fairly complete.
Force/release/assign/deassign syntax now works properly, allowing for
more sophisticated test bench design and debugging.
Bug fixes have been numerous and varied. This release of Icarus
Verilog is considerably more robust then previous versions, thanks to
diligent testing and bug reporting by users all over the world.
Add a new USE_LIBTOOL definition that uses the libtool package instead of
pkglibtool which is now considered outdated.
USE_PKGLIBTOOL is available for backwards compatibility with old packages
but is deprecated for new packages.
changes since last packaged snapshot are (from the authors announcements):
Icarus Verilog 20000527 Snapshot
----------------------------------
It's snapshot time!
<ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20000527.tar.gz>
This snapshot doesn't add any new features, but fixes a few bugs. I've
taken care of a bunch of bug reports with an eye towards getting this
polished up for a 0.3 stable release.
I fixed some problems with elaborating the condition expression of a
ternary operator. This was a long-standing bug that only happened in
structural (i.e. continuous assignment) situations.
I've also done some merging of event expressions. The netlist format makes
NetEvProbe and NetEvent objects for event expressions, and it was making
more then were needed. I've done some merging, though I have some more
things I can do on this front. I'll be working on it for the next snapshot.
I found a whole bunch of bugs with parsing expression lists, for example
module port expressions. The result is actually a smaller parser:-) So
module port expressions should be parsed and elaborated correctly, now.
In the vvm code generator, I've found some room to optimize the generated
code. I detect duplicate initialization of a nexus, and prevent the
excess code being generating. In one slightly degenerate example sent to
me, this change reduced the generated C++ by more then 6 times. I was
pretty amazed.
I've also slightly optimized the special case of behavioral assignments
from simple signal expressions. This removed a few lines of generated
code per assignment. This sort of thing helps compile time performance.
Icarus Verilog 20000512 Snapshot
----------------------------------
This is mostly a bug fix snapshot. No new features here, but I'm starting
to buff it up shiny for an upcoming 0.3 release. It looks like I'll be
starting to do release candidates soon, so test this snapshot hard, folks!
<ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20000519.tar.gz>
I re-implemented flip-flop and RAM synthesis, the new technique should
allow me to make much more complete synthesis. It's still not the nifty
full-scale synthesis I hope to do some day, but it should catch some of
the bigger synthesis problems.
I've also added to XNF synthesis the ability to detect start-up initial
values for flip-flip devices. This causes it to generate INIT= properties
for the devices as appropriate.
I've improved the VVM code generated by the t-vvm code generator. I've
managed to reduce the size of the code generated for some larger models
by 30%, and I should have improved run-time performance in the process.
This should help.
I've also found (thanks to bug reports) and fixed some module port issues.
I bet you can't dream up legal port binding that Icarus Verilog can't
handle:-) This issue should be taken care of.
VPI now includes the ability to set registers. I needed this to implement
a PNG image I/O module. I'm still working on that, I'll distribute it
separately when it is in better shape.
Various other bug fixes in iverilog and elsewhere. Several bug fixes
in the VVM runtime, including some support for the % operator.
I've done some updates to documentation to reflect some of the changes
since 0.2, so you can take a look at that too.
changes from the last packaged snapshot (from the authors announcement):
---------------Icarus Verilog 20000506 Snapshot------------------
A lot of internal reworking has been done on this, so there might be
problems with things like symbol binding. But I think this is much better
then the last snapshot. I am once again starting to think about a
stable release. I'll shoot for the end of May, so if there is anything
you want to see in that release, start pestering me.
The big job has been a rewrite of the symbol table that holds signals.
The previous elaboration and lookup code for signals/memories did not
work properly when hierarchical names were used in the context of tasks
and functions. Also, the old table kept all the signals is a single
lookup table that failed to take advantage of knowledge of the current
scope.
All that is changed. signals are now elaborated after parameters and
before processes, so all hierarchical accesses should work properly now,
no matter how contorted. I've also fixed some bugs with function/task
parameter passing.
I've also added some infrastructure for supporting system functions, and
I've added an implementation of the $random system function. This currently
uses the native random(3) C library function, but once I get access to the
standardized algorithm, I'll implement that.
There are also a few fixes to elaboration of ternary operators. They were
a bit touchy about result bit widths.
A few preprocessor bugs have been fixed, especially related to the
`ifdef/`endif tokens. People are all the sudden starting to use the
Icarus Verilog preprocessor, so some long-standing bugs have been caught.
The iverilog command had a few path problems fixed, and the remaining
necessary switches have been added. I really encourage people to start
using iverilog in place of verilog. The test suite now uses iverilog to
run the compiler, so should you. There is a man page.
The many bug fixes and changes since the last packaged snapshot
are (from the authors announcements):
Icarus Verilog 20000428 Snapshot
--------------------------------
This one clears up some pretty nasty and subtle bugs. If you've been
sending me bug reports, you're probably turning blue holding your breath
in anticipation of this snapshot. Breath in, Breath out.
Hooray, both force and release work properly. I'm happy about that,
release worked out a bit easier then I expected. These should be useful
to test bench designers.
The big news this past week, however, has been bug fixes. Lots of bug
fixes. I got lots of bug reports and I killed pretty nearly all of
them. There were lots of nasty icky problems with passing parameters
to/from tasks, especially when memory words were involved. I fixed up
a whole bunch of these, and now parameter passing should work pretty
will, modulus the few remaining bugs I'm not seeing yet.
The iverilog command is in better shape now, and I encourage people
to use it in place of the older "verilog" driver script. There is a
man page for iverilog, and it supports all the switches needed to do
simulation and synthesis. I would like people to start getting this
driver well tested and the bugs worked out, because it is going to be
the main driver come the next stable release.
Some neat new XNF features are happening. I synthesize identity compare
in XNF, and a few other missing operators. But the really neato part is
that I've taught Icarus Verilog to generate PIN records for module
ports, so that you can make XNF macros out of Verilog source. If you
elaborate a module that has ports, the XNF code generator will automatically
generate the necessary symbols so that external XNF tools can link the
generated output into larger designs. I've compared the XNF files from
Icarus Verilog with those generated by Abel, and they appear the same
to my eyes.
Icarus Verilog 20000421 Snapshot
--------------------------------
Bunches of bug fixes, and a few new features come with this snapshot.
This snapshot makes headway in both simulation and synthesis. I'm
also starting to make a big dent in my todo list for the 0.3 release.
The bunches of little bug fixes in this snapshot are a direct result of
bunches of bug reports this past week that I was able to deal with. If
you've been reporting bugs, this may contain your fix.
I redesigned the process implementation in the vvm backend, so the generated
code is a bit cleaner, and threads are lighter weight. And while I was at
it, fork/join now should work properly. I know there were a bunch of you
out there asking for this, so here it is.
I've incorporated into this release improved runtime support for integer
multiplication, it should now work now matter how incredibly enormous
you make the operands. Thanks to Chris Lattner for contributing the generic
multiply.
I've improved synthesis somewhat, there were some expressions in some
contexts that were not getting synthesized by the -Fsynth functor. This
is fixed, and I'm also starting to add some XNF specific optimizations
into the -Fxnfio functor. I do sensible things with identity compare,
for example.
I've added the program ``iverilog'' to be a new driver program written
in C instead of as a shell script. This driver supports the -tnull,
-txnf and -tvvm targets, as well as the -E flag that causes only the
preprocessor to be run. This should be interesting to those of you who
are looking for a working preprocessor. I'm still working on the -D and
the -I flags, but I expect this program to replace the verilog.sh script
before the 0.3 release.
Icarus Verilog 20000414 Snapshot
--------------------------------
All event handling is now complete. Yet another subject is behind me, and
on I go. By complete, I mean that named events, edge triggers, wait, and
lists of events all work. This took a little longer then I expected, so
some of the other things I wanted to work on had to wait.
As a side effect of event and thread scheduling work, I changed the way
that threads are generated in vvm. The result is that threads should be
a little faster at run time, and a lot faster at compile time. A *LOT*
faster at compile time. (Apparently, Verilog XL is still considerably
faster, but hey, I'm working on it.)
