Issues found with existing distfiles:
distfiles/eclipse-sourceBuild-srcIncluded-3.0.1.zip
distfiles/fortran-utils-1.1.tar.gz
distfiles/ivykis-0.39.tar.gz
distfiles/enum-1.11.tar.gz
distfiles/pvs-3.2-libraries.tgz
distfiles/pvs-3.2-linux.tgz
distfiles/pvs-3.2-solaris.tgz
distfiles/pvs-3.2-system.tgz
No changes made to these distinfo files.
Otherwise, existing SHA1 digests verified and found to be the same on
the machine holding the existing distfiles (morden). All existing
SHA1 digests retained for now as an audit trail.
---------------
Version 3.0.4: Jul 16th, 2015
Library:
Improve cross-compile for Android using Android NDK.
Support cross-compile for AArch64 Android (with Linux GCC).
Removed osxkernel_inttypes.h due to license issue (incompatible with BSD license).
Now it is possible to compile with CC having a space inside (such as "ccache gcc")
X86:
Fix a null pointer dereference bug on handling code with special prefixes.
Properly handle AL/AX/EAX operand for OUT instruction in AT&T syntax.
Print immediate operand in positive form in some algorithm instructions.
Properly decode some SSE instructions.
PowerPC:
Fixed some memory corruption bugs.
Mips:
Fixed instruction ID of SUBU instruction.
Fixed a memory corruption bug.
Arm:
Fixed a memory corruption bug on IT instruction.
XCore:
Fixed a memory corruption bug when instruction has a memory operand.
Python:
Support Virtualenv.
setup.py supports option --user if not in a virtualenv to allow for local usage.
Properly handle the destruction of Cs object in the case the shared library was already unloaded.
---------------
Version 3.0.3: May 08th, 2015
[ Library ]
- Support to embed into Mac OS X kernel extensions.
- Now it is possible to compile Capstone with older C compilers, such as
GCC 4.8 on Ubuntu 12.04.
- Add "test_iter" to MSVC project.
[ X86 ]
- All shifted instructions SHL, SHR, SAL, SAR, RCL, RCR, ROL & ROR now support
$1 as first operand in *AT&T* syntax (so we have "rcll $1, %edx" instead of
"rcll %edx").
- CMPXCHG16B is a valid instruction with LOCK prefix.
- Fixed a segfault on the input of 0xF3.
[ Arm ]
- BLX instruction modifies PC & LR registers.
[ Sparc ]
- Improved displacement decoding for sparc banching instructions.
[ Python binding ]
- Fix for Cython so it can properly initialize.
- X86Op.avx_zero_mask now has c_bool type, but not c_uint8 type.
- Properly support compile with Cygwin & install binding (setup.py).
---------------
Version 3.0.2: March 11th, 2015
[ Library ]
- On *nix, only export symbols that are part of the API (instead of all
the internal symbols).
[ X86 ]
- Do not consider 0xF2 as REPNE prefix if it is a part of instruction encoding.
- Fix implicit registers read/written & instruction groups of some instructions.
- More flexible on the order of prefixes, so better handle some tricky
instructions.
- REPNE prefix can go with STOS & MOVS instructions.
- Fix a compilation bug for X86_REDUCE mode.
- Fix operand size of instructions with operand PTR []
[ Arm ]
- Fix a bug where arm_op_mem.disp is wrongly calculated (in DETAIL mode).
- Fix a bug on handling the If-Then block.
[ Mips ]
- Sanity check for the input size for MIPS64 mode.
[ MSVC ]
- Compile capstone.dll with static runtime MSVCR built in.
[ Python binding ]
- Fix a compiling issue of Cython binding with gcc 4.9.
----------------
Version 3.0.1: February 03, 2015
[ X86 ]
- Properly handle LOCK, REP, REPE & REPNE prefixes.
- Handle undocumented immediates for SSE's (V)CMPPS/PD/SS/SD instructions.
- Print LJUMP/LCALL without * as prefix for Intel syntax.
- Handle REX prefix properly for segment/MMX related instructions (x86_64).
- Instruction with length > 15 is consider invalid.
- Handle some tricky encodings for instructions MOVSXD, FXCH, FCOM, FCOMP,
FSTP, FSTPNCE, NOP.
- Handle some tricky code for some X86_64 instructions with REX prefix.
- Add missing operands in detail mode for PUSH , POP , IN/OUT reg, reg
- MOV32ms & MOV32sm should reference word rather than dword.
[ Arm64 ]
- BL & BLR instructions do not read SP register.
- Print absolute (rather than relative) address for instructions B, BL,
CBNZ, ADR.
[ Arm ]
- Instructions ADC & SBC do not update flags.
- BL & BLX do not read SP, but PC register.
- Alias LDR instruction with operands [sp], 4 to POP.
- Print immediate operand of MVN instruction in positive hexadecimal form.
[ PowerPC ]
- Fix some compilation bugs when DIET mode is enable.
- Populate SLWI/SRWI instruction details with SH operand.
[ Python binding ]
- Fix a Cython bug when CsInsn.bytes returns a shorten array of bytes.
- Fixed a memory leak for Cython disasm functions when we immaturely quit
the enumeration of disassembled instructions.
- Fix a NULL memory access issue when SKIPDATA & Detail modes are enable
at the same time.
- Fix a memory leaking bug when when we stop enumeration over the disassembled
instructions prematurely.
- Export generic operand types & groups (CS_OP_xxx & CS_GRP_xxx).
Rytarowski.
Capstone is a disassembly framework with the target of becoming
the ultimate disasm engine for binary analysis and reversing in
the security community.
Capstone supports multiple hardware architectures, including ARM,
ARM64 (ARMv8), Mips, PPC, Sparc, SystemZ, XCore and X86 (including
X86_64).
