LLVM 15.0.5 is now available. This release is a bug-fix release and is API and ABI compatible with 15.0.0. If there are no major issues found with this release, then it will be the last 15.0.x release.
LLVM 15.0.4
Changes to the LLVM IR
LLVM now uses opaque pointers. This means that different pointer types like i8*, i32* or void()** are now represented as a single ptr type. See the linked document for migration instructions.
Renamed llvm.experimental.vector.extract intrinsic to llvm.vector.extract.
Renamed llvm.experimental.vector.insert intrinsic to llvm.vector.insert.
The constant expression variants of the following instructions have been removed:
extractvalue
insertvalue
udiv
sdiv
urem
srem
fadd
fsub
fmul
fdiv
frem
Added the support for fmax and fmin in atomicrmw instruction. The comparison is expected to match the behavior of llvm.maxnum.* and llvm.minnum.* respectively.
callbr instructions no longer use blockaddress arguments for labels. Instead, label constraints starting with ! refer directly to entries in the callbr indirect destination list.
Changes to building LLVM
Omitting CMAKE_BUILD_TYPE when using a single configuration generator is now an error. You now have to pass -DCMAKE_BUILD_TYPE=<type> in order to configure LLVM. This is done to help new users of LLVM select the correct type: since building LLVM in Debug mode is very resource intensive, we want to make sure that new users make the choice that lines up with their usage. We have also improved documentation around this setting that should help new users. You can find this documentation here.
Changes to Loop Optimizations
Loop interchange legality and cost model improvements
Changes to the AMDGPU Backend
8 and 16-bit atomic loads and stores are now supported
Changes to the ARM Backend
Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures.
Added support for the Armv8.1-M PACBTI-M extension.
Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures.
Added support for the Armv8.1-M PACBTI-M extension.
Removed the deprecation of ARMv8-A T32 Complex IT blocks. No deprecation warnings will be generated and -mrestrict-it is now always off by default. Previously it was on by default for Armv8 and off for all other architecture versions.
Added a pass to workaround Cortex-A57 Erratum 1742098 and Cortex-A72 Erratum 1655431. This is enabled by default when targeting either CPU.
Implemented generation of Windows SEH unwind information.
Switched the MinGW target to use SEH instead of DWARF for unwind information.
Added support for the Cortex-M85 CPU.
Added support for a new -mframe-chain=(none|aapcs|aapcs+leaf) command-line option, which controls the generation of AAPCS-compliant Frame Records.
Changes to the DirectX Backend
DirectX has been added as an experimental target. Specify -DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=DirectX in your CMake configuration to enable it. The target is not packaged in pre-built binaries.
The DirectX backend supports the dxil architecture which is based on LLVM 3.6 IR encoded as bitcode and is the format used for DirectX GPU Shader programs.
Changes to the PowerPC Backend
Common PowerPC improvements: * Add a new post instruction selection pass to generate CTR loops. * Add SSE4 and BMI compatible intrinsics implementation. * Supported 16-byte lock free atomics on PowerPC8 and up. * Supported atomic load/store for pointer types. * Supported stack size larger than 2G * Add __builtin_min/__builtin_max/__abs builtins. * Code generation improvements for splat load/vector shuffle/mulli, etc. * Emit VSX instructions for vector loads and stores regardless of alignment. * The mcpu=future has its own ISA now (FutureISA). * Added the ppc-set-dscr option to set the Data Stream Control Register (DSCR). * Bug fixes.
AIX improvements: * Supported 64 bit XCOFF for integrated-as path. * Supported X86-compatible vector intrinsics. * Program code csect default alignment now is 32-byte. * Supported auxiliary header in integrated-as path. * Improved alias symbol handling.
Changes to the RISC-V Backend
A RISCVRedundantCopyElimination pass was added to remove unnecessary zero copies.
A RISC-V specific CodeGenPrepare pass was added.
The machine outliner was enabled by default for RISC-V at -Oz. Additionally, the newly introduced RISCVMakeCompressible pass will make modify instructions prior to emission at -Oz in order to increase opportunities for the compression with the RISC-V C extension.
Various bug fixes and improvements to code generation for the RISC-V vector extensions.
Various improvements were made to RISC-V specific optimisation passes such as RISCVSExtWRemoval and RISCVMergeBaseOffset.
llc now computes the target ABI based on the target architecture using the same logic as Clang if not explicit ABI is given.
generic is now recognized as a valid CPU name and is mapped to generic-rv32 or generic-rv64 depending on the target triple.
Support for the experimental Zvfh extension was added, enabling half-precision floating point in vectors.
Support for the Zihintpause (Pause Hint) extension.
Assembler and disassembler support for the Zfinx and Zdinx (float / double in integer register) extensions.
Assembler and disassembler support for the Zicbom, Zicboz, and Zicbop cache management operation extensions.
Support for the Zmmul extension (a subextension of the M extension, adding multiplication instructions only).
Assembler and disassembler support for the hypervisor extension and for the Sinval supervisor memory-management extension.
Changes to the X86 Backend
Support half type on SSE2 and above targets following X86 psABI.
Support rdpru instruction on Zen2 and above targets.
During this release, half type has an ABI breaking change to provide the support for the ABI of _Float16 type on SSE2 and above following X86 psABI. (D107082)
The change may affect the current use of half includes (but is not limited to):
Frontends generating half type in function passing and/or returning arguments.
Downstream runtimes providing any half conversion builtins assuming the old ABI.
Projects built with LLVM 15.0 but using early versions of compiler-rt.
When you find failures with half type, check the calling conversion of the code and switch it to the new ABI.
Changes to the LLVM tools
(Experimental) llvm-symbolizer now has --filter-markup to filter Symbolizer Markup into human-readable form.
llvm-objcopy has removed support for the legacy zlib-gnu format.
llvm-objcopy now allows --set-section-flags src=... --rename-section src=tst. --add-section=.foo1=... --rename-section=.foo1=.foo2 now adds .foo1 instead of .foo2.
New features supported on AIX for llvm-ar:
AIX big-format archive write operation (D123949)
A new object mode option, -X , to specify the type of object file llvm-ar should operate upon (D127864)
Read global symbols of AIX big archive (D124865)
New options supported for llvm-nm:
-X, to specify the type of object file that llvm-nm should examine (D118193)
--export-symbols, to create a list of symbols to export (D112735)
The LLVM gold plugin now ignores bitcode from the .llvmbc section of ELF files when doing LTO. https://github.com/llvm/llvm-project/issues/47216
llvm-objcopy now supports 32 bit XCOFF.
llvm-objdump: improved assembly printing for XCOFF.
llc now parses code-model attribute from input file.
Changes to LLDB
The “memory region” command now has a “–all” option to list all memory regions (including unmapped ranges). This is the equivalent of using address 0 then repeating the command until all regions have been listed.
Added “–show-tags” option to the “memory find” command. This is off by default. When enabled, if the target value is found in tagged memory, the tags for that memory will be shown inline with the memory contents.
Various memory related parts of LLDB have been updated to handle non-address bits (such as AArch64 pointer signatures):
“memory read”, “memory write” and “memory find” can now be used with addresses with non-address bits.
All the read and write memory methods on SBProccess and SBTarget can be used with addreses with non-address bits.
When printing a pointer expression, LLDB can now dereference the result even if it has non-address bits.
The memory cache now ignores non-address bits when looking up memory locations. This prevents us reading locations multiple times, or not writing out new values if the addresses have different non-address bits.
LLDB now supports reading memory tags from AArch64 Linux core files.
LLDB now supports the gnu debuglink section for reading debug information from a separate file on Windows
LLDB now allows selecting the C++ ABI to use on Windows (between Itanium, used for MingW, and MSVC) via the plugin.object-file.pe-coff.abi setting. In Windows builds of LLDB, this defaults to the style used for LLVM’s default target.
Other Changes
The code for the LLVM Visual Studio integration has been removed. This had been obsolete and abandoned since Visual Studio started including an integration by default in 2019.
Added the unwinder, personality, and helper functions for exception handling on AIX. (D100132) (D100504)
PGO on AIX: A new implementation that requires linker support (__start_SECTION/__stop_SECTION symbols) available on AIX 7.2 TL5 SP4 and AIX 7.3 TL0 SP2.
* AI_V4MAPPED is not defined on NetBSD, so conditionalize its use.
* Force the use of pkgsrc GCC (here we require >= gcc 10) so that
<ISO_Fortran_binding.h> is made available to the C compiler.
* Sort PLIST.
The result builds and installs on amd64 and i386, but not on powerpc
due to Fortran's "real128" not being available there (CPU limitation).
This is a long overdue update with some refinements, notably
default-on f90 option.
We skipped some major releases, so please excuse me not including
the whole changelog. See https://open-mpi.org for more information.
This also removes the MPI_PREFIX business. No parallel installation of multiple
MPIs intended right now. Also, the f90 option is default now to support upcoming
parallel-computing packages in the default setup.
===============================================================================
Changes in 3.4.3
===============================================================================
# Fix bugs in GPFS ROMIO driver
# Fix bugs in DAOS ROMIO driver
# Fix nemesis shm bug on systems with weak memory consistency
# Fix progress issue in ch4:ucx finalize
# Fix nonblocking collective issue during finalize
# Fix UBSan warnings in 32-bit builds
# Fix predefined datatype handle leaks
# Fix bug in topology-aware communicator creation
# Fix Slurm nodelist parsing
# Fix testcase for out-of-tree configuration
# Fix truncation testcase for possible disconnection error
# Hydra help message improvements
# Add support for DAOS pool and container labels
===============================================================================
Changes in 3.4.2
===============================================================================
# Update configure options to support --disable-ze and --disable-cuda
to explicitly disable GPU-awareness
# Update embedded hwloc to version 2.4.1. Fixes a build issue on
systems with OpenCL.
# Fixes for Argobots thread package support.
# Fixes for the DAOS ROMIO driver (thanks to Intel for contributing)
# Fix additional bugs in GPU-aware nonblocking op collectives
# Fix 'make check' errors with embedded MPL and json-c libraries
# Fix support for GNI provider in ch4:ofi netmod
# Fix bug in dynamic window memory registration with ch4:ofi netmod
# Fix bug in persistent pt2pt when used with MPI_PROC_NULL
# Fix bug in hydra nameserver when freeing published entries
# Fix bugs in GPFS ROMIO driver (thanks to IBM for contributing)
# Fix bug in darray type creation (thanks to IBM for contributing)
# Fix bugs in XPMEM support
# Fix bug in MPI_Comm_spawn_multiple where non-root args were not ignored
===============================================================================
Changes in 3.4.1
===============================================================================
# Fix bug in GPU memory hooks that caused failures with NCCL
# Fix bug in GPU-aware nonblocking op collectives
# Hide symbols from embedded json-c module
# Removed anonymous struct/union usage in MPL
# Disable Java support in embedded UCX module
===============================================================================
Changes in 3.4
===============================================================================
# ch4 replaces ch3 as the default device configuration. If no network
module is specified at configuration-time, MPICH will search the
user environment in order to select one to build. The user will be
prompted to choose if no preferred network library is detected.
# Add support for Yaksa datatype engine (default in ch4).
# Add support for GPU buffers (CUDA, Level Zero) in pt2pt,
collectives, and one-sided communication.
# Add support for XPMEM.
# Add support for multiple virtual communication interfaces for more
efficient MPI_THREAD_MULTIPLE (experimental).
# Add DAOS ADIO driver to ROMIO (contributed by Intel).
# Add Quobyte ADIO driver to ROMIO (contributed by Quobyte).
# Add support for Arm compiler toolchain
# Add support for NVIDIA HPC compilers
# Add support for flang/f18 Fortran compiler
# Add support for AddressSanitizer and UndefinedBehaviorSanitizer to
debug configuration
# Remove mxm, llc, and portals4 netmods from ch3.
# Remove support for logical reduction operations on floating point
types.
# Remove MPIX_Mutex interfaces.
# Further improvements to ch4 business card exchange: extra
long address support and fixes for PMIx integration.
# Un-inline non-critical ch4 code for improved build times.
# Fix several test program bugs.
# Fix several static analysis and compiler warnings.
# Change the signature of MPID_Init to include requested and provided
thread levels.
===============================================================================
Changes in 3.3.2
===============================================================================
# Add support for struct sockaddr in MPICH, Hydra, and PMI socket
code. Works with both IPv4 and IPv6 addresses.
# Fix localhost detection on FreeBSD and macOS, avoiding long delay
during startup.
# Fix thread-local storage detection.
# Fix several test program bugs.
# Fix several static analysis and compiler warnings.
===============================================================================
Changes in 3.3.1
===============================================================================
# Fix bug in MPI_Testany/MPI_Waitany that could cause deadlock
# Add missing functionality in Argobots library support
# Fix configure-time detection for thread local storage support
# Better support for reproducible builds. Thanks to Bernhard
Wiedemann for the report and fixes
# Fix support for XL compiler toolchain
# Add support for -static-intel linking option
# Fix building on systems without weak symbols
# Fix several static analysis and compiler warnings
===============================================================================
Changes in 3.3
===============================================================================
# CH4 Device: A new device layer implementation designed for low software
overheads. CH4 has experimental support for OFI and UCX network libraries,
and POSIX shared memory. Thanks to Intel, Mellanox, and RIKEN AICS for
participating in the CH4 coding effort.
# Fixed SLURM integration in Hydra for new node list format.
# Added support for PMIx (https://pmix.github.io/pmix/) client
library in CH4 netmods. Note that you must use a compatible PMIx
server in this configuration.
# Better organization of collectives in the MPI layer. The new
scheme, which de-couples implementation from selection logic,
enables easier integration of additional algorithms.
# TSP collectives framework: A C++-template style framework for
collective algorithms is added to allow single collective
implementation to move data over generic or device-specific
transport functions.
# Improvements to derived datatype testing (DTPools -
https://wiki.mpich.org/mpich/index.php/DTPools).
# Added new "non-catastrophic" error codes to expose internal
resource exhaustion.
# Added info hints to MPI_Comm_split_type to support splitting
communicators by machine topology. Both on-node (socket, core,
etc.) and off-node (switch-level) hints are defined.
# Improvements to MPI_THREAD_MULTIPLE in CH4 through new thread safety
models at the Virtual Network Interface (VNI) level. This introduces two
new models that leverage work-queues to offload operations and improve
scalability under contention.
# Message Driven Thread Activation (MDTA). An alternative locking
model is defined for MPI_THREAD_MULTIPLE in CH4.
# Added PMI usage optimizations for business card exchange in CH4
netmods.
# Improvements on MPI_Abort. MPI_Abort invoked on subcommunicators will
only abort the connected processes within that communicator.
`
# Cleanup of whitespace (ch3 excluded) using the
maint/code-cleanup.sh script. For instructions on how to update
PRs/branches based on MPICH before the cleanup, see
https://github.com/pmodels/mpich/wiki/Code-Cleanup-Procedure.
# Removed the PAMI device and poe PMI client.
# C99 compiler support is now required to build MPICH.
# Several other minor bug fixes, memory leak fixes, and code cleanup.
A full list of changes is available at the following link:
http://git.mpich.org/mpich.git/shortlog/v3.2..v3.3
A list of bugs that have been fixed is available at the following
link:
https://github.com/pmodels/mpich/milestone/25?closed=1
This works around a subtle bug in github.mk.
Long story short is GITHUB_PROJECT is used to infer WRKSRC when github.mk
is in use. In addition, GITHUB_PROJECT is inferred from DISTNAME when
not explicitly set by the package.
If one wants to reference WRKSRC in a BUILDLINK_TRANSFORM, that breaks
because cwrappers.mk is evaluated before bsd.fetch.mk and GITHUB_PROJECT
is not yet known at that point, leading to an invalid WRKSRC expansion.
The only change is MPI 3.1 from 2 (labeled as "implemented or in
short-term development", so that's not wrong).
Add a note that the pkgsrc version is old and is MPI 3.0 (by
inspection from mpi.h).
The binaries have the WRKDIR in strings, printed via the -info
argument to show how it was built. (I don't understand how this is
buidling for anyone else.)
oneTBB 2021.5.0
What's New
Reworked synchronization mechanism to reduce contention when multiple task_arena’s are used concurrently.
Fixed sporadic memory corruption.
Enabled Microsoft Visual Studio* 2022 and Python 3.9 support.
Preview features
Extended task_group interface with a new run_and_wait overload to accept task_handle.
Fixed Issues
Fixed possible correctness issue in queuing_rw_mutex on non-Intel platforms.
Fixed GCC* 11 warnings.
Fixed sporadic memory corruption.
8.4.0 is a small release, with some bugfixes and improvements to the release process.
Bugfixes:
- (`%px`) only skip redisplay of streamed errors if outputs are complete
Compatibility improvements:
- Avoid use of recently deprecated asyncio/tornado APIs
around 'current' event loops that are not running.
Build improvements:
- Switch to hatch backend for packaging
Changes:
- fix require() wrapper to return all values returned by original require()
- Lanes no longer relies on malloc/free for internal allocations, but uses the primary alloc function from the master Lua state (excepted for LuaJIT flavors, because the allocator seems to assume that it won't be used oustide the Lua state).
- __lanesclone is now called only once with 3 parameters dest, source, size -> BREAKS CUSTOM DEEP USERDATA API
8.2.0 is a small release, mostly of small bugfixes and improvements.
Changes:
`len(AsyncMapResult)` and progress ports now use the number of items in the map,
not the number of messages.
Enhancements:
- Show output prior to errors in `%%px`
Bugs fixed:
- Fix cases where engine id could be `-1` in tracebacks
- Add missing `pbs` to engine launcher entrypoints
