pkglint --only "https instead of http" -r -F
With manual adjustments afterwards since pkglint 19.4.4 fixed a few
indentations in unrelated lines.
This mainly affects projects hosted at SourceForce, as well as
freedesktop.org, CTAN and GNU.
Local changes:
- set LICENSE (gnu-gpl-v2)
- replace DEPENDS of verilog to blk3
- stop replacing shebang for WISH - no longer needed
- stop helping to find tclConfig.sh and tkConfig.sh - no longer needed
- comment rationale for -DUSE_INTERP_RESULT (TCL/TK compatibility)
- drop patch-src_lxt2__read.c - fixed upstream (differently)
- comment and regenerate patch-src_lxt2__read.h
Upstream changelog (partial changes prior 0.7 not known)
==================
0.7.10
Stable release covered-0.7.10 made. This release updates the FST library to the latest version which contains some fixes and enhancements.
Stable release covered-0.7.9
11/21/2010 01:03 AM Filed in: Releases
Stable release covered-0.7.9 made. This release is a bug fix and minor feature enhancement release. Here are the details:
Cleaned up error messages emitted from the clang utility.
Updated GUI to use the ttk styled widgets for a more uniform look and allows the user to change the overall look of the GUI using a preference item.
Handling issue where a CDD file was created in a different directory and we attempt to load it in a different environment. Previously, a stack trace was emitted rather than just the user error message.
Updated copyright dates to include 2010
Added FST dumpfile scoring (new -fst option added to the score command to accommodate this option).
Adding support for "wire real" and associated code to Verilog parser.
Fixing issue with memory coverage.
Fixing bug 3054545. When a merged CDD file was used in an exclude command, a segmentation fault would occur.
Added support for constant assignment to reals.
Added support for "parameter integer" and "parameter real".
Added parsing support for the $fopenw system task.
Added support for performing +: and -: part selection on the left-hand-side of assignment expressions.
Fixed various memory overrun and memory leak issues that caused instability issues within the GUI.
Fixed GUI combinational logic issue where incorrect highlighting/underlining was occurring for uncovered expressions.
Fixed GUI issue with next/previous button traversal for combinational logic.
Enhanced the regression suite to verify all of the new features mentioned above.
Updated user guide HTML output to include the Covered banner to the top of each page.
User guide and man pages have been updated per these changes.
On a side note, active work on Covered's development branch(es) has stopped indefinitely. I plan to support the current feature set in the 0.7.x branch with possible minor enhancements as requested. Please feel free to continue to send me e-mail and/or submit bug reports against the 0.7.x stable releases.
Stable release covered-0.7.8
03/24/2010 10:20 PM Filed in: Releases
Stable release covered-0.7.8 made. This release is primarily a bug fix release, but it does contain a few new
minor features and Verilog language enhancements. Here are the details:
Fixed bug 2912587. Using the -f option with the merge command was causing errors.
Fixed bug 2912679. If the GUI was invoked (i.e., covered report -view) and an error in command-line parsing occurred, Covered segfaulted.
Added ability to specify the CDD on the report command-line when starting the GUI (i.e., covered report -view foobar.cdd) which will automatically load the specified CDD files into the GUI on startup. Feature request 2912698.
Fixed bug 2925756. An expression surrounded by the parenthesis could cause a segmentation fault when parsing.
Support has been added for NC-Verilog VPI usage.
Fixed bug 2926579. Changing from a known value to an X value should cause no change in toggle coverage; however, when we transition back to a known value and it differs from the previously known value, we record a toggle coverage change. Example: 0 -> X -> 0 (no change in coverage), 0 -> X -> 1 (change in coverage).
Fixed bug 2927285. Segmentation faults could occur when excluding FSM and combinational logic cases.
Added support for the $clog system function call.
Fixed bug 2929948. Assignments to a concatentation of signals could lead to segmentation fault.
Fixed issue in the LXT2 reader that resulted in a memory leak.
Fixed bug 2933112. Added full support for out-of-bounds assignment.
Added new -T global option that provides a "terse" output which outputs the Covered header and warnings/errors only (less output than using none of the global output verbosity options). Feature request 2952492.
Fixed bug 2960887. Adds support for creating a definition which contains no user value (i.e., `define FOO). Covered was incorrectly assigning a value of 1 to these types of defines.
Fixed bug 2958529. Zero width replications are now supported by Covered (i.e., {0{a & b}})
Fixed bug 2974860. Fixed issue with FSM state input/output variables being output to an ASCII report file correctly.
Added ability to allow the "trans" parameter to Covered FSM attributes to contain additional characters after it. Some simulators don't like Verilog attributes having the same name for multiple parameters. Feature request 2976039.
User guide has been updated per these changes.
Development release covered-20091126
11/26/2009 10:10 PM Filed in: Releases
Development release covered-20091126 made. This is a bug fix release only.
Stable release covered-0.7.7
10/24/2009 10:09 PM Filed in: Releases
Stable release covered-0.7.7 made. This is a bug fix release only.
Fixed compilation warnings when compiling on 64-bit Mac OS X and Debian-based platforms.
Updates to build scripts to help downstream Debian releases builds.
Fixed bug 2880705. $Id: keywords containing newlines are now handled properly. Additionally, fixing issues with multiply instantiated modules within a generate block.
Fixed bug 2881869. Fixed a stack overflow issue in the gen_item_resolve function that would cause segmentation faults when too many items were being generated within a single generate block.
Fixed bug 2882433. Fixed the "ERROR! Parameter used in expression but not defined in current module" error when a generated module instance has a parameter override of a parameter with the same name as the parameter within the module that contains the generate block.
Stable release covered-0.7.6
08/24/2009 10:12 PM Filed in: Releases
Stable release covered-0.7.6 made. This is a bug fix release only.
Fixed misspelling in report generator code (misspelling showed up in text reports)
Fixed issues with performing module merging with modules containing generate blocks configured differently for different instantiations of the same module.
Stable release covered-0.7.5
08/02/2009 10:20 PM Filed in: Releases
Stable release covered-0.7.5 made. This is a bug fix release only.
Fixed bug 2808818. If a generate variable name collided with a reg/wire name, Covered was not emitting an error.
Fixed bug 2808820. If no signal was used from the dumpfile and at least one signal needs information from the dumpfile, Covered needed to signal a user error.
Fixed bug 2812321. Parameterized/generated modules could get incorrect coverage calculated for them.
Fixed bug 2812495. Fixed a crash issue. There is another part to this bug report that is not fixed, however.
Fixed bug 2813405. A design run with the -g score option caused the GUI to freeze when viewed.
Fixed bug 2813948. Fixed assertion issue with merging scored and unscored CDD files.
Development release covered-20090802
08/02/2009 10:19 PM Filed in: Releases
Development release covered-20090802 made. This development release adds several performance enhancements and bug fixes to the new inlined code coverage flow, including the following:
Adding support for $random and $urandom system calls to inlined coverage.
Includes all fixes made to the stable 0.7.5 release.
Adding support for $value$plusargs system calls to inlined coverage.
Fixing issue with generated IF statements.
Added user documentation for inlined coverage flow and score options.
Fixing issue with generated code interrupting comma-separated assign statements.
Performed code simplification and performance improvement with the way statements were handled internally.
Removed unnecessary calls to simulation functions when using inlined code coverage (this added a performance penalty).
Improved performance of inlined code generator for sizing generated signals.
Fixed memory indexing issues related to memory coverage.
Added support for static function and static ternary operators for inlined code coverage.
Added code to differentiate functions used statically and not to do the right thing for inlined code coverage accumulation.
Added vcd_diff script which checks the dumpfile output from non-inlined and inlined design files to verify that the inlined code generator does not change the result. This check is now a part of all inlined regression runs.
Made several performance improvements to the VCD file reader. The reader is now 10-20% faster.
Added support for Verilator regressions runs and ported a couple of diagnostics to Verilator format.
Adding check to make sure that a CDD file without inlined mode set that reads a VCD file containing inlined coverage data emits an error to the user and exits gracefully.
Added -inline-comb-depth score option to allow the user to specify a shallower combinational coverage depth to be generated -- improving inlined simulation and coverage performance.
For Verilator runs, inserted pragmas around intermediate combinational logic expression signals to exclude them from being output to VCD files. This improves simulation and coverage performance for Verilator runs (other simulators that have a VPI that automatically remove these signals from generating change callbacks).
Performing code replace of some actual code with pre-calculated intermediate expression values for further simulation performance improvements.
Added "e" option to -inline-metrics which allows event coverage to be turned on/off independently of other combinational logic coverage. This allows further simulation and coverage performance improvements (especially for Verilator runs).
Added optimization that causes code generation to be skipped for assertion files when assertion coverage is not required.
Full regressions now runs cleanly with all code changes.
Stable release covered-0.7.4
06/17/2009 10:21 PM Filed in: Releases
Stable release covered-0.7.4 made. This is a bug fix release only.
Updated regression files for the new 2.4 version of the OVL.
Fixed bug 2804585. Memory reads in LHS part selects were not being marked for memory coverage.
Fixed issue with VPI usage in a VCS simulation with generate statements.
Fixed bug 2805191. Automatic tasks/functions that manipulate variables outside of the task/function can cause incorrect toggle coverage for those signals.
Fixed bug 2806855. Generate blocks generating module instantiations could lead to score command errors (segfaults, internal assertion errors, etc.)
Stable release covered-0.7.3
06/04/2009 10:22 PM Filed in: Releases
Stable release covered-0.7.3 made. This primarily fixes a few bugs in the compile of Covered "out of the box". It seems that even with the regression testbench, things can still slip through the cracks :( Anyhow, please use this release instead of the 0.7.2 release.
Stable release covered-0.7.2
05/09/2009 10:23 PM Filed in: Releases
Stable release covered-0.7.2 made. This is primarily a bug fix release with a few new features added to the CLI. Here are the details of the changes.
Fixed bug 2791651. Memory deallocation errors occurred when syntax errors were being reported by the parser.
Fixed bug 2791599. Whitespace prior to a `line or #line directive were not being handled properly.
Fixed bug 2794588. If a module was specified in a -v option after its directory was specified by the -y option to the score command, the module was not found for parsing.
Fixed bug 2794684. If a normal (not generate) case statement within a generate block will output the case expression to be output to the CDD more than once, leading to internal assertion errors when the CDD file is read.
Fixed bug 2795088. When a CDD file is opened from the wizard GUI window, the open file window can be placed behind the wizard window. Instead the wizard window should disappear once a selection button has been clicked.
Fixed bug 2795086. If the user clicked on the global exclusion reason listbox when it is empty, a Tcl/Tk error message box was raised.
Fixed bug 2795089. If the GUI detailed combinational logic window is used to view several expressions one after the other, Covered can segfault.
Fixed bug 2795583. Score command segfaults when a module is instantiated within a generate block and overrides a parameter value within the module.
Fixed bug 2795640. Variables instantiated within a generate block caused issues with Covered when simulated with VCS.
Fixed bug where memory elements being assigned via non-blocking assignments were not being evaluated, leading to incorrect coverage output.
CLI updates/fixes:
When the 'debug on' command is specified, a line specifying that the debug mode is now on is output (previously nothing was output (because the debug mode was off).
Changed the 'debug on' command to 'debug less' and 'debug more' where the prior only outputs the executed statements and timestep information during simulation while the latter outputs what 'debug on' used to output (extremely verbose).
Fixed bug 2795209. When an unknown CLI command was specified, a memory error occurred.
Fixed bug 2795215. Status bar was attempting to be output during simulation when debug mode was turned on. This created some unreadable/messy output.
Changed the 'goto ' command to 'goto time '.
Added 'goto line [:]' command which simulates until the specified line number is about to be simulated.
Added 'goto expr ' command which simulates until the given expression evaluates to a value of true.
Added support for handling the Ctrl-C interrupt when the score command is simulating with the -cli option specified. In this case, simulation will immediately stop and return a CLI prompt which will allow the user to continue interacting with the simulation.
Updated user guide documentation to include the changes made to the CLI.
Stable release covered-0.7.1
05/07/2009 10:24 PM Filed in: Releases
Stable release covered-0.7.1 made. This is a bug fix release only. Here are the details:
Fixed bug 2782473. CDD files being merged from different testbenches but with similar leading hierarchy (but different top-level modules) which would lead to internal assertion errors.
Fixed bug 2785453. Wires declared in generated named scopes were not handled correctly by Covered in VPI mode of operation, leading to inaccurate coverage information.
Fixed bug 2786986. An always block with a part select in the sensitivity list was triggering on the entire signal change rather than the specific part select, leading to a potential degradation in performance and inaccuracy in coverage information.
Allow time variable types to be included for coverage.
Fixing permission issue with the install-sh script that some people would get after first downloading and installing.
Updated README and INSTALL files to be more accurate.
Fixed coverage accuracy issue for code that uses variable part selects in LHS of expressions.
Stable release covered-0.7
04/26/2009 10:24 PM Filed in: Releases
Stable release covered-0.7 made. This is a significant improvement over the 0.6 release, providing Verilog language enhancements, significant score optimizations, new rank and exclude commands, an enhanced merging capability, a multitude of GUI enhancements, a complete overhaul of the user documentation, many bug fixes, and much more.
to address issues with NetBSD-6(and earlier)'s fontconfig not being
new enough for pango.
While doing that, also bump freetype2 dependency to current pkgsrc
version.
Suggested by tron in PR 47882
* 08/30/2006
Stable release covered-0.4.7 made. This release is mostly a bug fix release with two feature
additions. The new feature is the global -B option was performs name obfuscation on all identifying,
design-sensitive names from all output (with the exception of CDD file output). This option is
mostly useful as a way to share debugging information with the maintainer(s) of Covered without giving
away sensitive information. Additionally, the -rI score option was added to allow user's to completely
skip the race condition checking phase. This allows users to force Covered to consider all code for
coverage (if race condition checking is performed, all code considered to be potential race conditions
are automatically excluded from coverage consideration). User documentation has been updated for these
changes. The following lists the changes in this release.
- Fixed bug 1535412. Implicit event expressions (i.e., "always @*") now traverse named begin/end
blocks correctly to search for RHS variables.
- Fixed bugs related to segmentation faults and memory leak issues
- Fixed hierarchical reference search to match Verilog-1995 LRM
- Fixed bug 1538922. If -vcd or -lxt option was specified twice, an incorrect error message was
displayed to the user.
- Added -rI option to allow user's to bypass the race condition checking step in the score command.
- Fixed bug 1538920. Handling of any-edge triggered events (i.e., "@(b)") was incorrectly handled
by Covered. Additionally, fixed the event trigger operator (->) to work correctly with the new
changes.
- Fixed bug 1541944. Command options that require a value are now checked to make sure that a value
exists, and an appropriate error message is output if this is not achieved.
- Fixed bug 1542454. Command options that must only be allowed once on a command-line are now
checked and handled appropriately (caused a segmentation fault previously).
- Fixed bug 1544322. When an AND- or OR-type expression has either a left or right expression evaluate
to 0 or 1, respectively, Covered now outputs correct coverage information when the opposite expression
evaluates to an X or Z value, simultaneously.
- Fixed bug 1544325. Multi-variable expressions are now always output as such in report files.
- Fixed bug 1544169. Avoiding consideration of named begin/end block keywords in line coverage.
- Fixed bug 1546059. Covered now properly handles the removal of statement blocks that cannot be
considered for coverage which also contain parameters from another functional unit block.
- Fixed bug with connection of statements in a statement block.
- Updated documentation to match new features added in this release.
* 07/22/2006
Stable release covered-0.4.6 made. This release contains several bug fixes that are listed below.
- Fixed segmentation fault bug which occurs when a multi-bit select on the LHS contains any
expression besides static values.
- Fixed several memory leaks found with valgrind
- Fixed bug 1520159 - arrays of instances incorrectly always started at index 0.
- Fixed bug 1521598 having to do with reduction unary invert and logical not operators not
calculating correctly.
- Fixed bug in db_read when a functional unit is being merged to point to the used module.
- Fixed assertion in link.c such that no segmentation fault occurs if a string is not found
in a str_link list for deletion.
- Fixed bug pertaining to embedded concatenations within function/task parameter lists.
- Fixed bug pertaining to empty named begin-end blocks.
- Fixed bug in the db_read function that would cause Covered to flag an internal assertion
error if an error occurred while reading the CDD file and the global -D option was specified.
- Fixed upwards name referencing bug (1524705).
- Enhanced regression suite to verify that all of these bugs are properly fixed.
* 07/08/2006
Stable release covered-0.4.5 made. This release contains a bug fix to properly handle cases
where two or more signals are declared with a parameter in their range field (i.e., reg [FOO:0] a, b;)
This caused Covered to segfault due to attempting to free the same address twice. Bug 1518932.
Also contains a bug fix to properly remove statement blocks that contain case, casex or casez
expressions and unbindable expressions.
* 5/28/2006
Stable release covered-0.4.4 made. This release contains a bug fix to proper handle hierarchical
referencing of parameter values. This feature was technically not supported in the past but caused
an internal assertion error when this was performed. The feature is now fully supported.
* 4/21/2006
Stable release covered-0.4.3 made. This release contains a bug fix to the statement connection function that
caused segmentation faults during the score command. Also added support for big endian wires/regs. This
information was being ignored by the parser and, consequently, was not being handled correctly by Covered's
internal simulator, leading to incorrect coverage information. The lack of this support was also causing
an internal error in the memory allocation routine when scoring the dumpfile.
* 4/17/2006
Stable release covered-0.4.2 made. This release contains a bug fix that caused an assertion error in the
binding.c source file to occur. The reason for this assertion was a syntax error in the parser that caused
problems when more than one task call was made in a statement block. Also added support for multi-line
definitions (i.e., a '\' character used at the end of a definition line). This was missing but was not meant
to be missing.
* 4/4/2006
Stable release covered-0.4.1 made. This release contains one bug fix that causes an assertion error when
compiling designs that use a concatenation operation on the left-hand-side of assignment statements. If
you are experiencing this problem with the 0.4 release, it is recommended that you use this new release
instead.
* 3/29/2006
Stable release covered-0.4 made. In addition to all of the features, optimizations and bug fixes
that have gone into the development releases from the 0.3 stable release, the following features, updates
and bug fixes have been added.
- Fixed bug with a statement connection issue that causes lines of code to be not considered for
coverage that should have been.
- Fixed bug in report command where combinational expressions were not being output to match the original
Verilog code.
- Added CDD file viewer window to GUI to allow the user to see which CDD files are currently loaded/merged.
- Fixed bug in combinational logic verbose viewer which caused the window to resize dependent upon
the location of the cursor (this was an annoyance)
- Changed the output of simple combinational logic to change to unary combinational logic output if either
the left or the right expression was a constant value (eliminates unachievable combinational logic cases
from being output leading to more accurate coverage results).
- Removed combinational expressions that contain only constant values from being considered for coverage.
- Updated simple combinational logic output in reports to be as concise as possible for AND and OR type
expressions.
- Removed duplication of information in CDD files for race conditions.
- Fixed bug in GUI dealing with showing race conditions
- Fixing bug in GUI pertaining to the next/previous buttons in the combinational logic detail viewer. Previously,
clicking on one of these buttons would only advance you to the next uncovered line. Now it will advance
you to the next uncovered statement.
- Updated development, user and GUI documentation to reflect the above changes and to bring them up-to-date
with the rest of the tool.
Please see the ChangeLog file for all changes made from the 0.3 stable release to the 0.4 stable release.
Lots of enhancements, features, optimizations, bug fixes, performance improvements and documentation improvements
are contained in this stable release, making it very worth while for any Covered users to get their hands on
it.
around at either build-time or at run-time is:
USE_TOOLS+= perl # build-time
USE_TOOLS+= perl:run # run-time
Also remove some places where perl5/buildlink3.mk was being included
by a package Makefile, but all that the package wanted was the Perl
executable.
Changes since the last stable release:
- User-specified FSM code coverage. By using command-line options or inline code specified
by the user, FSM code coverage can be extracted from the design. This does not include
the ability to automatically extract FSMs from the design (an ability that will be added
in future stable releases).
- Enhanced performance of the score command. A 3x - 5x speedup in the running time of the
score command on the design should be expected with this release over past stable releases.
- Enhanced readability of coverage reports. The coverage report look has been overhauled to
produce a much more readable/understandable coverage report.
- Several bug-fixes have been made, including coverage number calculation bugs.
- Development and user documentation updates.
- Enhanced regression suite.
From the NEWS file:
This release is basically a 0.2.1 release with the available bug fixes
patches applied to it. This should make getting a stable release less
tedious.
Covered is a Verilog code coverage analysis tool that can be useful
for determining how well a diagnostic test suite is covering the
design under test. Typically in the design verification work flow, a
design verification engineer will develop a self-checking test suite
to verify design elements/functions specified by a design's
specification document. When the test suite contains all of the tests
required by the design specification, the test writer may be asking
him/herself, "How much logic in the design is actually being
exercised?", "Does my test suite cover all of the logic under test?",
and "Am I done writing tests for the logic?". When the design
verification gets to this point, it is often useful to get some
metrics for determining logic coverage. This is where a code coverage
utility, such as Covered, is very useful.
Please note that this package is for a stable release version.
There is a seperate package (covered-current) which is made of
development snapshots.
