redefines about which buildlink.mk files would care is BUILDLINK_X11_DIR,
which points to the location of the X11R6 hierarchy used during building.
If x11.buildlink.mk isn't included, then BUILDLINK_X11_DIR defaults to
${X11BASE} (set in bsd.pkg.mk), so its value is always safe to use. Remove
the ifdefs surrounding the use of BUILDLINK_X11_DIR in tk/buildlink.mk and
revert changes to move x11.buildlink.mk before the other buildlink.mk files.
changes since last snapshot include:
- addition of a fpga target for synthesis. outputs edif, optimized for
xilinx virtex parts.
- fixed bug with synthesis of !=
- fixed bug in hex constant parsing
- fixed vvp bug with subtracting very wide words
- much improved VCD output
- many other bug fixes and robustness improvements.
use X11_BUILDLINK_MK as a test value. Generally just reordering the
inclusions so that x11.buildlink.mk comes before the other buildlink.mk
files will make everthing work.
New in 20011020:
- better measurement: value at both cursors or difference in values at cursors
- enhanced handling of log scales
- yet more file-reading improvements and general bug fixes
foo-* to foo-[0-9]*. This is to cause the dependencies to match only the
packages whose base package name is "foo", and not those named "foo-bar".
A concrete example is p5-Net-* matching p5-Net-DNS as well as p5-Net. Also
change dependency examples in Packages.txt to reflect this.
Changes include:
- add the ability to specify gain in terms of voltage gain _or_ power gain
- add input/output resistance keywords
- add defaults keyword to allow users to change program defaults on the fly
- the cascade-mode for emacs now works for fontlock
- add voltage output levels in addition to the power levels
- add a verbose style comment (ie, one which gets copied to the output file
instead of being simply ignored).
- new homepage and master ftp site.
The previous version had no known bugs. Hopefully this one won't either.
to ${X11BASE} in the header and library search paths into references to
${LOCALBASE}/share/x11-links. These packages should now be strongly-
buildlinked regardless of whether xpkgwedge is installed.
Changes well-tested on NetBSD-1.5X/i386 with and without xpkgwedge and
lightly-tested on NetBSD-1.5.1/alpha without xpkgwedge.
* The Big Change: VVP
Past versions of Icarus Verilog performed simulation by compiling the
Verilog design to intermediate C++ code, then in turn compiling that
C++ (usually with G++) to a binary executable. This program was then
executed to actually run the simulation.
The 0.5 compiler, however, uses a custom internal language called
"vvp." The vvp code generator writes a program in the vvp language
that the vvp interpreter executes. This gets runtime performance
similar to the older vvm method, but compile times are much faster.
The result of this change is that there is a new program, ``vvp'',
that is installed with the existing ``iverilog'' compiler. This
program actually executes the simulation generated by the vvp code
generator.
There are manual pages for the iverilog command and the new vvp
command, as well as a QUICK_START document to help you run your first
simulation.
* What Else Is New
The compiler itself is now a lot more robust. While it still does not
compile and understand the entire IEEE1364 standard, the compiler is
less likely to crash on bad input, gives better error messages, and
has generally been cleaned up.
------------------
ACS 0.29 release notes (06/30/2001)
The primary effort has been to implement IBIS, which is still not
done. The changes here are mostly infrastructure changes needed to
support IBIS.
New features:
1. "Fit" function has choice of fit order and extrapolation. You can
have order 0, 1, 2, or 3.
2. "Posy" has even and odd options, to determine what happens in the
negative region.
3. Modelgen improvements. It now is useful for the whole device,
sometimes. It now handles probes and the device side of the model.
The diode uses it completely. There are still a few missing features
needed for the MOSFET and BJT.
4. Spice-3 compatible semiconductor resistor and capacitor.
5. "Table" model statement.
Improvements, bug fixes, etc.
1. Option "numdgt" really works.
2. Better error messages from modelgen.
3. Code changes for optimization of commons. This should reduce
memory use, sometimes, by sharing commons. Common sharing is still
not fully implemented.
4. Fix two bugs that sometimes caused problems after a "modify" or on
a "fault".
5. Better handling of "vmin" and "vmax". It should be much less
likely that limiting causes convergence to a nonsense result.
Some things that are still partially implemented:
1. Internal element: non-quasi-static poly-capacitor.
2. BSIM models, charge effects, "alpha0" parameter. (computed then ignored)
changes are:
-----------
RELEASE NOTE FOR ICARUS VERILOG 20010630
I've done some cleanup of the mingw port of Icarus Verilog. I've also
added instructions for how to build Icarus Verilog under mingw. I'm
working on making that the preferred way to support Windows, and when
I make the 0.5 release I will make Windows binaries this way. Anyhow,
feedback on the build instructions and the build results using the
instructions in mingw.txt are welcome.
I've make "vvp" the default target type. The older vvm behavior is
available with the "-tvvm" flag to iverilog, but I would rather be
told about (and fix) bugs in the vvp code generator and run time.
I've added support for the (unsigned) right shift operator. The left
shift has been working for a while now, but right shift somehow
slipped through the cracks. The shift operators still don't quite work
in structural contexts, but they should show up sometime next week.
I've finally got VCD output working properly with vvp. It may even be
better then with vvm, although some internal symbols are still generated.
A few odd bugs have been fixed, including a code generation error for
xnf, and error checking of user defined function parameters.
CXXFLAGS, and LDFLAGS by the buildlink.mk files so remove the extra
definitions to add them from the package Makefiles. As advised by the
bsd.buildlink.mk file, also ensure that the buildlink.mk files are
included prior to defining any package-specific CFLAGS/LDFLAGS to ensure
that the buildlink directories are at the head of the compiler search
paths.
Use BUILDLINK_INCDIR, BUILDLINK_LIBDIR for locations of linked headers
and libraries. Create a variable BUILDLINK_TARGETS whose value is the
list of build-link targets to execute.
(2) Use devel/readline/Makefile.readline to get readline support, and note
why GNU readline is required.
(3) Make this package work with xpkgwedge...the app-defaults file was
always being installed under ${X11BASE}.
many changes since the last snapshot. Mostly they involve expanded
VVP support. The VVP target now passes >200 of the tests from the
test suite. While not as complete as the VVM target, VVP is getting
closer and its _much_ _much_ faster.
increase in version number. From the XCircuit homepage:
Note that the March 28, 2001 version corrects a bug due to
dubious C syntax causing segmentation violations when xcircuit
was compiled without the debug option.
C Trivia question:
What does "x[a] = x[--a]" do?
Answer A: "x[a] = x[a - 1]; a--"
Answer B: "a--; x[a] = x[a]"
Answer C: either A or B, depending on your OS, compiler version,
and/or debug or optimizer switch.
Changes since the last packaged snapshot from the authors announcements:
Icarus Verilog snapshot 20010422
--------------------------------
I've integrated a bunch of UDP patches from Stephan Boettcher. These
go to the core of ivl, so if you use Icarus Verilog with UDPs, you
might want to give this a test for us.
Stephan has also added some ivl_target support for UDP devices. This is a
prerequisite to vvp support for UDP devices.
Some of you have been beating me over the head about disable, so the
vvp target now supports disable. It only works in certain very constrained
situations, but the idea is there and the more common cases are simply a
matter of getting around to them. I actually could use more examples of
the use of disable for the test suite.
In the process, I have settled on the interaction of threads and scopes,
and changed the %fork syntax to match. See the README.txt and opcodes.txt
file for details. The implementation of %end and %join simplified in
the process.
The vvp-tgt code generator supports a few more gate types. New gate
types are pretty easy to add, it's just boring grunt work. That's why
they've been popping up slowly.
I've also got certain behavioral shifts working. Only constant shifts,
so far, but this covers a pretty large percentage of the real world
uses of shift, I think.
I fixed a few specify block parse problems, so it should ignore
even more complex specify blocks now:-) One of these days I really will
properly support specify blocks.
PROGRESS
I was hoping to get vvp up to a similar level as vvm by the end of
April, but that doesn't look like it's going to happen. I'm up to 182
tests passed, compared to 318 of Icarus Verilog/vvm, so I have a ways
to go yet. I see no real point to making a release until I get up to
300 or so tests passed. That is the goal for 0.5 release.
But of course if vvp is enough for you, then it is soooo much faster
then vvm.
Icarus Verilog 20010415 Snapshot
--------------------------------
As with all the most recent snapshots, this is almost entirely progress
with the vvp code generator and simulation engine. I'm up to 159 tests
passed in the test suite, so I'm getting there. But there's still plenty
to go.
I also fixed what appeared to be a minor problem with elaboration of ?:
expressions in continuous assignments. The code was actually fine, it
was a spurious assert. This fix affects vvm as well.
Icarus Verilog/vvp now support <= statemements with internal delays.
That is, "foo <= #10 bar;" should work properly, and there are tests
in the suite that prove it. This is a pretty common syntax, so this
should help a lot of folks.
I also fixed a bug in the code generator that would cause it to put a
constant bit as a destination for the bitwise boolean operators. This
caused run-time asserts.
The event or support in vvp has been extended to now support arbitrary
width, so now you can for example wit for any changes in a 32bit reg.
This handles most of the likely cases, so @ statements should now be
pretty generally functional.
The handling of run-time threads has been revamped in preparation for
support of the disable statement. It also plugs a memory leak where
fork/join and task/function calls are invoked. And this version should
also clean up all those tiny initial foo=bar threads that all programs
seem to have. Threads that are done are now freed, along with their
memory, hopefully reducing the runtime memory footprint.
That's pretty much it this time 'round. Working with threads took some
time, so the progress isn't as flashy as it sometimes is.
There is still lots to do with vvp before 0.5, but I would appreciate
any feedback you can offer. It's complete enough already that I'm able
to accept bug reports on it, even if it turns out to be a "not supported
yet" type of thing. At this point, I'd be curious to know what hangups
are preventing its regular use.
Surface Impedance Method for Interconnect Analysis.
SIMIAN is a two dimensional frequency dependent series
impedance extraction tool for inerconnects and transmission
lines using conductors of rectangular or circular cross section.
The use of the surface ribbon method (SRM) greatly enhances
the speed of computation relative to the volume filament
method (VFM).
