* 08/30/2006
Stable release covered-0.4.7 made. This release is mostly a bug fix release with two feature
additions. The new feature is the global -B option was performs name obfuscation on all identifying,
design-sensitive names from all output (with the exception of CDD file output). This option is
mostly useful as a way to share debugging information with the maintainer(s) of Covered without giving
away sensitive information. Additionally, the -rI score option was added to allow user's to completely
skip the race condition checking phase. This allows users to force Covered to consider all code for
coverage (if race condition checking is performed, all code considered to be potential race conditions
are automatically excluded from coverage consideration). User documentation has been updated for these
changes. The following lists the changes in this release.
- Fixed bug 1535412. Implicit event expressions (i.e., "always @*") now traverse named begin/end
blocks correctly to search for RHS variables.
- Fixed bugs related to segmentation faults and memory leak issues
- Fixed hierarchical reference search to match Verilog-1995 LRM
- Fixed bug 1538922. If -vcd or -lxt option was specified twice, an incorrect error message was
displayed to the user.
- Added -rI option to allow user's to bypass the race condition checking step in the score command.
- Fixed bug 1538920. Handling of any-edge triggered events (i.e., "@(b)") was incorrectly handled
by Covered. Additionally, fixed the event trigger operator (->) to work correctly with the new
changes.
- Fixed bug 1541944. Command options that require a value are now checked to make sure that a value
exists, and an appropriate error message is output if this is not achieved.
- Fixed bug 1542454. Command options that must only be allowed once on a command-line are now
checked and handled appropriately (caused a segmentation fault previously).
- Fixed bug 1544322. When an AND- or OR-type expression has either a left or right expression evaluate
to 0 or 1, respectively, Covered now outputs correct coverage information when the opposite expression
evaluates to an X or Z value, simultaneously.
- Fixed bug 1544325. Multi-variable expressions are now always output as such in report files.
- Fixed bug 1544169. Avoiding consideration of named begin/end block keywords in line coverage.
- Fixed bug 1546059. Covered now properly handles the removal of statement blocks that cannot be
considered for coverage which also contain parameters from another functional unit block.
- Fixed bug with connection of statements in a statement block.
- Updated documentation to match new features added in this release.
* 07/22/2006
Stable release covered-0.4.6 made. This release contains several bug fixes that are listed below.
- Fixed segmentation fault bug which occurs when a multi-bit select on the LHS contains any
expression besides static values.
- Fixed several memory leaks found with valgrind
- Fixed bug 1520159 - arrays of instances incorrectly always started at index 0.
- Fixed bug 1521598 having to do with reduction unary invert and logical not operators not
calculating correctly.
- Fixed bug in db_read when a functional unit is being merged to point to the used module.
- Fixed assertion in link.c such that no segmentation fault occurs if a string is not found
in a str_link list for deletion.
- Fixed bug pertaining to embedded concatenations within function/task parameter lists.
- Fixed bug pertaining to empty named begin-end blocks.
- Fixed bug in the db_read function that would cause Covered to flag an internal assertion
error if an error occurred while reading the CDD file and the global -D option was specified.
- Fixed upwards name referencing bug (1524705).
- Enhanced regression suite to verify that all of these bugs are properly fixed.
* 07/08/2006
Stable release covered-0.4.5 made. This release contains a bug fix to properly handle cases
where two or more signals are declared with a parameter in their range field (i.e., reg [FOO:0] a, b;)
This caused Covered to segfault due to attempting to free the same address twice. Bug 1518932.
Also contains a bug fix to properly remove statement blocks that contain case, casex or casez
expressions and unbindable expressions.
* 5/28/2006
Stable release covered-0.4.4 made. This release contains a bug fix to proper handle hierarchical
referencing of parameter values. This feature was technically not supported in the past but caused
an internal assertion error when this was performed. The feature is now fully supported.
* 4/21/2006
Stable release covered-0.4.3 made. This release contains a bug fix to the statement connection function that
caused segmentation faults during the score command. Also added support for big endian wires/regs. This
information was being ignored by the parser and, consequently, was not being handled correctly by Covered's
internal simulator, leading to incorrect coverage information. The lack of this support was also causing
an internal error in the memory allocation routine when scoring the dumpfile.
* 4/17/2006
Stable release covered-0.4.2 made. This release contains a bug fix that caused an assertion error in the
binding.c source file to occur. The reason for this assertion was a syntax error in the parser that caused
problems when more than one task call was made in a statement block. Also added support for multi-line
definitions (i.e., a '\' character used at the end of a definition line). This was missing but was not meant
to be missing.
* 4/4/2006
Stable release covered-0.4.1 made. This release contains one bug fix that causes an assertion error when
compiling designs that use a concatenation operation on the left-hand-side of assignment statements. If
you are experiencing this problem with the 0.4 release, it is recommended that you use this new release
instead.
* 3/29/2006
Stable release covered-0.4 made. In addition to all of the features, optimizations and bug fixes
that have gone into the development releases from the 0.3 stable release, the following features, updates
and bug fixes have been added.
- Fixed bug with a statement connection issue that causes lines of code to be not considered for
coverage that should have been.
- Fixed bug in report command where combinational expressions were not being output to match the original
Verilog code.
- Added CDD file viewer window to GUI to allow the user to see which CDD files are currently loaded/merged.
- Fixed bug in combinational logic verbose viewer which caused the window to resize dependent upon
the location of the cursor (this was an annoyance)
- Changed the output of simple combinational logic to change to unary combinational logic output if either
the left or the right expression was a constant value (eliminates unachievable combinational logic cases
from being output leading to more accurate coverage results).
- Removed combinational expressions that contain only constant values from being considered for coverage.
- Updated simple combinational logic output in reports to be as concise as possible for AND and OR type
expressions.
- Removed duplication of information in CDD files for race conditions.
- Fixed bug in GUI dealing with showing race conditions
- Fixing bug in GUI pertaining to the next/previous buttons in the combinational logic detail viewer. Previously,
clicking on one of these buttons would only advance you to the next uncovered line. Now it will advance
you to the next uncovered statement.
- Updated development, user and GUI documentation to reflect the above changes and to bring them up-to-date
with the rest of the tool.
Please see the ChangeLog file for all changes made from the 0.3 stable release to the 0.4 stable release.
Lots of enhancements, features, optimizations, bug fixes, performance improvements and documentation improvements
are contained in this stable release, making it very worth while for any Covered users to get their hands on
it.
around at either build-time or at run-time is:
USE_TOOLS+= perl # build-time
USE_TOOLS+= perl:run # run-time
Also remove some places where perl5/buildlink3.mk was being included
by a package Makefile, but all that the package wanted was the Perl
executable.
Changes since the last stable release:
- User-specified FSM code coverage. By using command-line options or inline code specified
by the user, FSM code coverage can be extracted from the design. This does not include
the ability to automatically extract FSMs from the design (an ability that will be added
in future stable releases).
- Enhanced performance of the score command. A 3x - 5x speedup in the running time of the
score command on the design should be expected with this release over past stable releases.
- Enhanced readability of coverage reports. The coverage report look has been overhauled to
produce a much more readable/understandable coverage report.
- Several bug-fixes have been made, including coverage number calculation bugs.
- Development and user documentation updates.
- Enhanced regression suite.
From the NEWS file:
This release is basically a 0.2.1 release with the available bug fixes
patches applied to it. This should make getting a stable release less
tedious.
Covered is a Verilog code coverage analysis tool that can be useful
for determining how well a diagnostic test suite is covering the
design under test. Typically in the design verification work flow, a
design verification engineer will develop a self-checking test suite
to verify design elements/functions specified by a design's
specification document. When the test suite contains all of the tests
required by the design specification, the test writer may be asking
him/herself, "How much logic in the design is actually being
exercised?", "Does my test suite cover all of the logic under test?",
and "Am I done writing tests for the logic?". When the design
verification gets to this point, it is often useful to get some
metrics for determining logic coverage. This is where a code coverage
utility, such as Covered, is very useful.
Please note that this package is for a stable release version.
There is a seperate package (covered-current) which is made of
development snapshots.
