Many improvements since the last packaged version including, but not limited
to:
- enhanced transient timestep control algorithm which is significantly more
accurate than spice now.
- enhanced compatibility with hspice netlists
- named nodes (as opposed to numbered only nodes) work now
- improvements to the bsim3v3 model support
- migration from a custom build system to a GNU autoconf/automake based build
system.
in the process. (More information on tech-pkg.)
Bump PKGREVISION and BUILDLINK_DEPENDS of all packages using libtool and
installing .la files.
Bump PKGREVISION (only) of all packages depending directly on the above
via a buildlink3 include.
Gnucap 0.34 release notes (02/01/2004)
This is a bug fix and compatibility release.
1. Fix bug causing incorrect interpolation of backwards tables.
2. Fix tanh overflow bug.
3. Fix some parsing bugs.
4. Fix occasional "double load" bug.
5. Fix AC sweep with one point.
6. Transient start time really works.
7. Fix occasional assert fail after option short is changed.
8. Fix memory leak resulting from failure to delete unused common.
9. Fix a Z probe bug that sometimes gave wrong answers.
10. Fix a limiting bug that sometimes caused non-convergence.
11. Configure handles isnan.
12. Improvements to logic initialization. It is still not correct.
Some things that are still partially implemented:
1. BSIM models, charge effects, "alpha0" parameter. (computed then
ignored)
2. Configure still doesn't handle everything.
3. The model compiler still requires too much raw coding.
4. Named nodes. If you set the option "namednodes", it will support
named nodes, but some things don't work, so it is off by default.
5. The preliminary IBIS code is now included. For now, it is a
standalone executable, that reads an IBIS file and generates a
netlist. The netlist requires some editing to use, and is not fully
compatible anyway. It is included in hopes of recruiting help in
finishing the project.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. An occasional bogus calculation in MOSFETS occurs when a device is
reversed. This sometimes causes nonconvergence.
3. Initialization is strange when repeating an analysis without an
intermediate edit.
Hot items for a future release (no promises, but highly probable):
1. Verilog-AMS and VHDL-AMS support.
rather than using LOWER_OPSYS. This is because the couple of os's
that had correct targets were the same and others that pkgsrc works on
aren't listed at all (like solaris). Fixes build problems noted on
solaris.
Gnucap 0.33 release notes (01/12/2003)
This is a bug fix and compatibility release.
0.32 was not widely distributed due to password problems and a heavy
work load, so the release notes are repeated after the current ones.
New features:
1. Add inductance probes, like capacitor.
Bug fixes:
1. Fix xprobe duplicate default arg bug - shows in g++3.2.
2. Fix bug that sometimes caused a crash when changing a model after
analysis.
3. Fix bug that caused an assert to fail (debug build) after removing
a probe from an element.
4. Fix a dumb typo hack bug ddHAS_READLINE. Now history and command
line editing really works. It was working, but somehow the hack
slipped into the release code.
=================================================================
Gnucap 0.32 release notes (09/30/2002)
New features:
1. Series resistance in the diode. It took 5 minutes to do,
so it is embarrasing that it wasn't done before.
2. History and command line editing, using Gnu Readline. Thanks to
Simon Hoffe for sending me the patch.
3. More parameters in the BJT model. This gives it better
compatibility with commercial simulators. These parameters are beyond
Spice 3f5.
4. "M" parameter in diode, BJT and MOS devices. M is the number of
parallel devices. Some commercial simulators have this.
Changes that may or may not be improvements.
1. The definition of the transient option "UIC" has changed. It is
now Spice compatible, which means to not attempt to do any solution or
consistency check. Just apply the values, assuming anything that
isn't specified is 0. The old behavior was to attempt a solution
while holding the IC values.
Bug fixes:
1. voltage sync bug. It still doesn't fix the MOS 2 convergence
problem.
2. Fix memory leak in POLY components.
3. Fix bug in Fourier that sometimes causes overrun (crash) and time
sync errors.
4. Modelgen: fix bug in list parsing.
5. Some changes to eliminate warnings when compiling with g++ 3.1.
6. Use Euler differentiation on first step, because trap used a value
that cannot be known then. Usually, this doesn't make much
difference, but there are a few cases where the error can get
magnified and trigger trapezoidal ringing, leading to a totally bogus
result. It most cases, you could hide it with small enough steps.
These cases should work with default settings now.
7. Fix bug that sometimes caused incorrect handling of initial
conditions (UIC),
8. Fix bug that caused continuing a transient analysis to give
incorrect results.
Significant internal changes:
1. The inductor uses all of the same support functions as the
capacitor, including "integrate", which is now correctly called
"differentiate".
2. Most of the code is in place for named nodes. It mostly works and
can be turned on with the option "namednodes". It is off by default
because it is not complete. Most likely, it will be finished in the
next release.
Some things that are still partially implemented:
1. BSIM models, charge effects, "alpha0" parameter. (computed then
ignored)
2. Configure still doesn't handle everything.
3. The model compiler still requires too much raw coding.
4. Named nodes. If you set the option "namednodes", it will support
named nodes, but some things don't work, so it is off by default.
5. The preliminary IBIS code is now included. For now, it is a
standalone executable, that reads an IBIS file and generates a
netlist. The netlist requires some editing to use, and is not fully
compatible anyway. It is included in hopes of recruiting help in
finishing the project.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. An occasional bogus calculation in MOSFETS occurs when a device is
reversed. This sometimes causes nonconvergence.
3. The "modify" command with multiple arguments seems to take only the
first one. It used to work, but is broken in this release. I am not
sure when it broke.
The most significant changes are the BJT model and "binning".
New features:
1. BJT model.
2. "Binning" for all MOS models.
3. Internal element: non-quasi-static poly-capacitor. (needed by BJT).
4. Enhancements to the data structures and model compiler to support
binning in general.
5. A line prefixed by "*>" is not ignored, in spite of the fact that
"*" usually begins a comment. This is a deliberate incompatibility
with Spice. If you prefix a line by "*>" it will be interpreted as a
non-comment in Gnucap, but a comment in Spice.
6. Circuit line prefixes of ">" and command prefixes of "-->" are
ignored. This is so you can copy and paste whole lines, without
having to manually remove the prompt string.
Changes that may or may not be improvements.
1. It is not the default to include stray resistance in device models.
The option "norstray" will revert to the old behavior. This is only a
change to the default value of "rstray".
Significant internal changes:
1. The internal element non-quasi-static poly-capacitor actually
works. It is used by the BJT model, and will eventually be used by
MOSFET models.
2. There are now two poly_g devices: "CPOLY_G" and "FPOLY_G". There
are interface differences that impact modeling. Previously, there was
only one, which is equivalent to the "FPOLY_G".
GnuCap is a general purpose circuit simulator. GnuCap was
formerly known as ACS. GnuCap performs nonlinear
dc and transient analyses, fourier analysis, and ac analysis
linearized at an operating point. It is fully interactive and
command driven. It can also be run in batch mode or as a server.
The output is produced as it simulates. Spice compatible models
for the MOSFET (level 1-7) and diode are included in this
release.
Since it is fully interactive, it is possible to make changes and
re-simulate quickly. The interactive design makes it well suited
to the typical iterative design process used it optimizing a circuit
design.
Unlike Spice, the engine is designed to do true mixed-mode
simulation. Most of the code is in place for future support of
event driven analog simulation, and true multi-rate simulation.
If you are tired of Spice and want a second opinion, you want to
play with the circuit and want a simulator that is interactive,
you want to study the source code and want something easier to
follow than Spice, or you are a researcher working on modeling
and want automated model generation tools to make your job easier,
try GnuCap.
