CXXFLAGS, and LDFLAGS by the buildlink.mk files so remove the extra
definitions to add them from the package Makefiles. As advised by the
bsd.buildlink.mk file, also ensure that the buildlink.mk files are
included prior to defining any package-specific CFLAGS/LDFLAGS to ensure
that the buildlink directories are at the head of the compiler search
paths.
Use BUILDLINK_INCDIR, BUILDLINK_LIBDIR for locations of linked headers
and libraries. Create a variable BUILDLINK_TARGETS whose value is the
list of build-link targets to execute.
(2) Use devel/readline/Makefile.readline to get readline support, and note
why GNU readline is required.
(3) Make this package work with xpkgwedge...the app-defaults file was
always being installed under ${X11BASE}.
many changes since the last snapshot. Mostly they involve expanded
VVP support. The VVP target now passes >200 of the tests from the
test suite. While not as complete as the VVM target, VVP is getting
closer and its _much_ _much_ faster.
increase in version number. From the XCircuit homepage:
Note that the March 28, 2001 version corrects a bug due to
dubious C syntax causing segmentation violations when xcircuit
was compiled without the debug option.
C Trivia question:
What does "x[a] = x[--a]" do?
Answer A: "x[a] = x[a - 1]; a--"
Answer B: "a--; x[a] = x[a]"
Answer C: either A or B, depending on your OS, compiler version,
and/or debug or optimizer switch.
Changes since the last packaged snapshot from the authors announcements:
Icarus Verilog snapshot 20010422
--------------------------------
I've integrated a bunch of UDP patches from Stephan Boettcher. These
go to the core of ivl, so if you use Icarus Verilog with UDPs, you
might want to give this a test for us.
Stephan has also added some ivl_target support for UDP devices. This is a
prerequisite to vvp support for UDP devices.
Some of you have been beating me over the head about disable, so the
vvp target now supports disable. It only works in certain very constrained
situations, but the idea is there and the more common cases are simply a
matter of getting around to them. I actually could use more examples of
the use of disable for the test suite.
In the process, I have settled on the interaction of threads and scopes,
and changed the %fork syntax to match. See the README.txt and opcodes.txt
file for details. The implementation of %end and %join simplified in
the process.
The vvp-tgt code generator supports a few more gate types. New gate
types are pretty easy to add, it's just boring grunt work. That's why
they've been popping up slowly.
I've also got certain behavioral shifts working. Only constant shifts,
so far, but this covers a pretty large percentage of the real world
uses of shift, I think.
I fixed a few specify block parse problems, so it should ignore
even more complex specify blocks now:-) One of these days I really will
properly support specify blocks.
PROGRESS
I was hoping to get vvp up to a similar level as vvm by the end of
April, but that doesn't look like it's going to happen. I'm up to 182
tests passed, compared to 318 of Icarus Verilog/vvm, so I have a ways
to go yet. I see no real point to making a release until I get up to
300 or so tests passed. That is the goal for 0.5 release.
But of course if vvp is enough for you, then it is soooo much faster
then vvm.
Icarus Verilog 20010415 Snapshot
--------------------------------
As with all the most recent snapshots, this is almost entirely progress
with the vvp code generator and simulation engine. I'm up to 159 tests
passed in the test suite, so I'm getting there. But there's still plenty
to go.
I also fixed what appeared to be a minor problem with elaboration of ?:
expressions in continuous assignments. The code was actually fine, it
was a spurious assert. This fix affects vvm as well.
Icarus Verilog/vvp now support <= statemements with internal delays.
That is, "foo <= #10 bar;" should work properly, and there are tests
in the suite that prove it. This is a pretty common syntax, so this
should help a lot of folks.
I also fixed a bug in the code generator that would cause it to put a
constant bit as a destination for the bitwise boolean operators. This
caused run-time asserts.
The event or support in vvp has been extended to now support arbitrary
width, so now you can for example wit for any changes in a 32bit reg.
This handles most of the likely cases, so @ statements should now be
pretty generally functional.
The handling of run-time threads has been revamped in preparation for
support of the disable statement. It also plugs a memory leak where
fork/join and task/function calls are invoked. And this version should
also clean up all those tiny initial foo=bar threads that all programs
seem to have. Threads that are done are now freed, along with their
memory, hopefully reducing the runtime memory footprint.
That's pretty much it this time 'round. Working with threads took some
time, so the progress isn't as flashy as it sometimes is.
There is still lots to do with vvp before 0.5, but I would appreciate
any feedback you can offer. It's complete enough already that I'm able
to accept bug reports on it, even if it turns out to be a "not supported
yet" type of thing. At this point, I'd be curious to know what hangups
are preventing its regular use.
Surface Impedance Method for Interconnect Analysis.
SIMIAN is a two dimensional frequency dependent series
impedance extraction tool for inerconnects and transmission
lines using conductors of rectangular or circular cross section.
The use of the surface ribbon method (SRM) greatly enhances
the speed of computation relative to the volume filament
method (VFM).
* Control Panel
- The Control Panel now has a "Tree View" which provides an
overview over all areas of EAGLE, like Libraries, User Language
Programs, Projects etc. The Control Panel's tree view supports
"Drag&Drop" to copy or move files and directories.
- Objects in the tree view have a context menu that can be
accessed by pressing the right mouse button.
- The menu option "Save project as..." is no longer available.
- New projects can now be created via the context menu in the
"Projects" tree item, or by selecting "File/New/Project" from
the Control Panel.
- The path settings in "Options/Directories" can now use the special
names "$HOME" and "$EAGLEDIR" to access the user's home directory
or the EAGLE installation directory, respectively.
- The new "Auto backup" feature will automatically save any modified
drawing into a safety backup file after a certain time.
* New Project Structure
- The names of files that are under the current project directory
are no longer written as absolute paths into the 'eagle.epf' file,
but rather relative to the project directory. This allows for
complete project directories to be easily copied or renamed.
- A project is now held in a subdirectory that contains a file
named 'eagle.epf' (which stores the location and settings of open
windows).
* User Interface
- The textual command menu can now be configured to display
aliased command buttons as well as submenus (see HELP MENU for
details).
- Changes made in the "Options/User interface" dialog now take effect
immediately for open editor windows.
- The cursor inside a layout or schematic editor window can now be
set to a "large" crosshair cursor (see "Options/User interface").
- The "Delete" icon was changed from a pencil with an eraser to
an 'X'.
- The "Split" icon was changed to better indicate what will happen.
* Keyboard and mouse control
- Alt-0 no longer popups up the window list, but leads directly to
the Control Panel.
- Pressing the Ctrl key while moving the mouse now scrolls the draw
window in any direction.
- The mouse wheel now zooms in and out in editor windows (zoom
factor can be adjusted in "Options/User interface/Mouse wheel
zoom", a value of '0' disables this feature and the sign of this
factor defines the direction of the zoom operation).
* Screen display
- The default for "minimum visible text size" has been changed to 3.
- The display mode parameter FAST has been dropped.
- By default the zoom factor in editor windows is limited so that
the resulting virtual drawing area does not exceed the 16-bit
coordinate range. This is necessary to avoid problems with
graphics drivers that are not 32-bit proof. If the graphics
driver on a particular system can handle coordinates that
exceeed the 16-bit range, "Options/User interface/Limit zoom
factor" can be switched off allow larger zoom factors.
* Design Rules
- EAGLE now supports a full set of Design Rules that are stored
inside the board file (and can also be saved to disk files).
Both the Design Rule Check and the Autorouter will use the
same set of rules.
- Newly created boards take their design rules from the file
'default.dru', which is searched for in the first directory
listed in the "Options/Directories/Design rules" path.
- Cream mask values are now measured "inwards" and thus have a
positive sign.
- The parameters AnnulusConduct and ThermalConduct are no longer
available. There are now checkboxes in the Design Rules dialog's
"Supply" tab that define whether a Thermal or Annulus symbol
shall have a "Restring" or not.
* Net Classes
- Nets and Signals now have a new parameter called "Net Class".
* Polygons
- When calculating polygons, the minimum distances defined in
the design rules and net classes will be taken into account.
* Design Rule Check
- The DRC now runs a lot faster.
- Progress is now displayed in a progress bar.
- Polygons from different signals with the same 'rank' are checked
against each other.
- The 'overlap' and 'minimum distance' check are no longer separate
checks.
- The DRC no longer checks an individual signal against everything
else. The newly introduced "Net Classes" can be used to do this.
- The rectangle for a selective DRC can now be defined with
"click&drag" (just as in the WINDOW command).
- Holes are no longer checked in the "Grid" check (only pads, vias,
smds and wires in signal layers are checked).
- Any objects in signal layers within a package are now checked
against each other.
* Long strings
- All names, values and texts can now be of any length.
- The User Language constants regarding name lengths still exist,
but the program uses these constants only for formatted output as
in the EXPORT command. They are still present for compatibility
only.
- There is no more limit to the number of members in a bus (bus
index values are limited to 0..511).
- Bus member names can now contain any characters, except
':', ',', '[', ']' and blanks.
* Wire styles
- Wires now have a new parameter 'Style', which can be set to one
of the following values:
Continuous _______________ (default)
LongDash ___ ___ ___ ___
ShortDash _ _ _ _ _ _ _ _
DashDot ___ . ___ . ___
- The variable for setting the bend type of a wire has been renamed
from Wires_Style to Wire_Bend to avoid confusing the two
parameters.
* Text fonts
- Texts can now have three different fonts: 'Vector' the program's
internal vector font (as used in previous versions)
'Proportional' a proportional pixel font (usually 'Helvetica')
'Fixed' a monospaced pixel font (usually 'Courier')
- When updating drawings from older versions, all texts are
converted to 'Proportional' font, except for those in layers
Top...Bottom, tRestrict and bRestrict, since these texts probably
need to be subtracted from signal polygons, which only works with
the 'Vector' font.
- The program makes great efforts to output texts with fonts other
than 'Vector' as good as possible. However, since the actual font
is drawn by the system's graphics interface, 'Proportional' and
'Fixed' fonts may be output with different sizes and/or lengths.
* Pads and Vias
- The diameter of pads and vias is now derived from the drill
diameter using the Design Rules (the pad and via diameter '0' is
now allowed and results in a diameter that is derived from the
current design rules). If a pad is defined with a diameter that
exceeds the one that would result from the current design rules,
the larger diameter is taken. The default value for the diameter
of newly created pads and vias is now '0' to allow the Design
Rules to define the actual diameters.
- Pads can have different shapes on Top and Bottom (they will always
be 'round' on the inner layers).
- The via shape now only applies to the outer layers (they will
always be 'round' on the inner layers).
- The diameter of pads with shape X/YLongOct now defines the
smaller side of the pad (formerly the wider side). Existing
files will be modified accordingly during the update.
- By default vias no longer generate Thermal symbols in supply
layers.
* Round SMDs
- SMDs have a new parameter "Roundness", which can range between
0 and 100 and defines the percentage by which the corners are
"rounded". A value of 0 (default) results in a rectangle, while
a value of 100 results in a circular shape (if the x and y
dimension of the SMD are the same), which can be used for BGAs.
- The SMD command accepts roundness values as numbers with a
leading '-' (to be able to distinguish it from the SMD size
values). The CHANGE command has a new option "Roundness".
* New Library structure
- What was called a "Device" in previous versions is now
called a "Device Set". A "Device Set" consists of the gate
definitions and several actual devices, implemented through
"Package Variants"
- The PACKAGE command can now assign several different package
variants to a device (as in 7400N, 7400D,...).
- The new command TECHNOLOGY can be used to define various
"technology" variants for a device's package variants (as in
74LS00N, 74S00N,...).
- The CHANGE command has the new options PACKAGE and TECHNOLOGY,
which can be used to select from the packages and/or technologies
a device set defines. This can be done from within the schematic
or board.
- The new command DESCRIPTION can be used to provide detailed
textual information about a device, package or library.
- The CONNECT dialog now allows copying pin/pad connections from
an other package variant. Only those package variants are offered
in the "Copy from" combo box that have the same pad names as the
current package variant (only connected pads are checked).
- The CONNECT dialog now asks the user if he want's to discard
any changes before cancelling the dialog.
- The CONNECT command can now handle gate names that contain
periods.
- The device editor now displays a list of package variants, a
preview of the current package and the description of the
device.
* Automatic Library update
- If a library has been modified after parts or packages from it
have been added to a schematic or board, the new command UPDATE
can be used to automatically update all used library objects with
their latest version (see "Help Update").
- The UPDATE command can be selected from the "Library" pulldown
menu in a board or schematic, or from the context menu of a
library in the Control Panel. It is also possible to drag&drop
a library from the Control Panel onto a schematic or board
drawing and perform the update that way.
* Bill Of Material
- The User Language Program 'bom.ulp' to generate the "Bill Of
Material" has been rewritten. It now has a dialog in which the
user can interactively generate the BOM, pulling in additional
data from a user defined database file. Use "RUN bom.ulp" and
click on the "Help" button for more information.
* Generating Outlines for milling prototypes
- The User Language Program 'outlines.ulp' can be used to generate
the data necessary to control a milling machine for generating
a prototype board.
* User Language
- The User Language now supports user defined dialogs as well as
standard file dialogs and message boxes.
- The RUN command now accepts additional arguments that are
available to the ULP as 'argc' and 'argv' parameters.
- Data can now be read into a ULP.
- The new lookup() function can be used to perform database
lookups.
- The new fileglob() function can be used to do a directory
search.
- The new fileerror() function can be used check for I/O errors.
- The 'exit()' function can now have a string parameter which is
sent to the editor window and executed as a command string.
- ULPs can now include other ULP files with the new #include
directive.
* Script files
- Script files can now call other scripts (as long as no
recursive call is made).
- Script files can now contain comments. Everything after
(and uncluding) a '#' character will be ignored.
- The 'eagle.scr' file is now first searched for in the current
project directory (which is equal to the current working
directory in case there is no project open) and then in the
directories listed in the Control Panel's
"Options/Directories/Scripts".
* Autorouter
- The Autorouter can now route "through" signal polygons (this
can be controlled by the new cost factor 'cfPolygon').
- The Autorouter control parameters are now stored inside the
board file. They can be saved to and loaded from external files
via the Autorouter dialog. Existing control files will be
automatically read and stored in the board file when updating
files from previous versions.
- The Autorouter and DRC now use the same set of Design Rules.
- When saving Autorouter control parameters to disk, the minimum
distance parameters are no longer part of that file.
- There can now be any number of 'Optimize' passes. By default
there are now 4 'Optimize' passes.
- Each pass can be separately activated or deactivated.
- The Autorouter can now route different wire widths and minimum
distances simultaneously by using "Net Classes".
- The minimum routing grid is now 0.02mm (about 0.8mil).
- The default control parameters and the internal handling of
cfChangeDir have been modified to avoid jagged tracks.
* ADD command
- The ADD command can now be used with wildcards ('*' or '?') to
find a specific device. The ADD dialog offers a tree view of
the matching devices, as well as a preview of the device and
package variant.
- To add directly form a specific library, the command syntax
ADD devicename@libraryname
can be used. 'devicename' may contain wildcards and
'libraryname' can be either a plain library name (like "ttl"
or "ttl.lbr") or a full file name (like
"/home/mydir/myproject/ttl.lbr" or "../lbr/ttl").
- If a device or package shall be added, and there is already
such an object (with the same name from the same library) in the
drawing, an automatic library update will be performed which
replaces the existing object in the drawing with the current
version from the library.
- The new command UPDATE can be used to update all parts in a board
or schematic with modified library versions (see "Help Update").
* CHANGE command
- CHANGE LAYER for wires and polygons now works between any
layers within packages and symbols.
* CONNECT command
- Pressing the SPACE key in the CONNECT dialog while a list element
has the focus will now perform the 'connect' or 'disconnect'
action, respectively.
* DELETE command
- If the last supply symbol of a given type is deleted from a net
segment that has the same name as the deleted supply pin, that
segment is now given a newly generated name (if there are no other
supply symbols still attached to that segment) or the name of one
of the remaining supply symbols.
* DISPLAY command
- The new parameters '?' and '??' can be used to control what
happens if a layer that is given in a DISPLAY command does not
exist in the current drawing. See "Help Display" for details.
* GROUP command
- If the selected group is empty, the GROUP command no longer
displays a message box saying "Group is empty". It rather prompts
that message in the status bar (with a beep) and stays active for
a new group definition.
* ERC command
- The ERC now lists the package names when reporting parts/
elements with inconsistent packages.
- The ERC now detects inconsistencies between the implicit power
and supply pins in the schematic and the actual signal
connections in the board.
- The ERC now checks for missing junctions and overlapping wires
and pins.
* ERRORS command
- The ERRORS dialog is no longer modal (it stays "on top" of the
editor window) and can be kept open while resuming normal
editing in the editor window. The various error types are now
listed more detailed.
* EXPORT command
- The EXPORT can now export image files (BMP, PNG, etc.). See
"Help/EXPORT" for details.
* NET and BUS command
- If a net wire is placed at a point where there is already
another net or bus wire or a pin, the current net wire will be
ended at that point (in previous versions the user had to click
twice to end a net wire).
* PASTE command
- When pasting objects into a drawing that already contains earlier
(different) versions of these objects, an automatic library
update will be performed which replaces the existing objects in
the drawing with the new versions from the paste buffer.
* PRINT command
- The PRINT dialog's "Page setup" now allows border values that
are smaller than the initial values derived from the printer
driver. To get back to the original default you can enter '0'.
* REMOVE command
- The REMOVE command can now handle device, symbol and package
names with extension (for example REMOVE name.pac).
* RENAME command
- The RENAME command now allows '.' in names.
- The RENAME command can now handle device, symbol and package
names with extension (for example RENAME name1.pac name2[.pac]
- note that the extension is optional in the second parameter).
* REPLACE command
- The REPLACE command can no longer be used with active forward-
and backannotation. This is due to the now complete definition
of a device set with all its package variants. Use the CHANGE
PACKAGE command to select one of the defined package variants,
or use the UPDATE command to update a package with a modified
version from the same library.
* SET command
- The SET options for Thermal and Annulus parameters as well as
the Solder Stop and Cream mask data have been removed.
- The SET variables DRC_SHOW and DRC_COLOR are now obsolete
(progress in the Design Rule Check is now displayed in a
progress bar).
- The SET variable MAX_ERROR_ZOOM is now obsolete. The ERRORS
dialog is no longer modal (it stays "on top" of the editor
window) and zooming can be done with the usual WINDOW commands
or buttons.
* SHOW command
- Highlighted objects are now kept highlighted during subsequent
window operations.
- Pressing ESCape in the SHOW command now lowlights the currently
highlighted object.
* USE command
- The USE command is now mainly for use in script files.
* CAM Processor
- The CAM Processor no longer supports matrix printers. Use the
PRINT command to print to the system printer.
- The CAM Processor no longer prints sheets. Use the PRINT
command instead.
* Parameter storage
- User specific parameters are now stored in an "eaglerc" file.
At program start, parameters are read (in the given sequence)
from the files
prgdir/eaglerc
/etc/eaglerc
$HOME/.eaglerc
where prgdir means the directory that contains the EAGLE program
file.
* Command line options
- The options '-A' and '-T' are now obsolete (thermal and annulus
data is now defined in the Design Rules).
- The options '-B' and '-M' are now obsolete (solder stop and
cream mask data is now defined in the Design Rules).
- The option '-C' is now obsolete, since the CAM Processor no
longer supports matrix printers (all printing is done with the
PRINT command).
- The options '-Z' and '-Y' are now obsolete (drill symbols are
configured in "Options/Set/Drill" and are stored in the user
specific "eaglerc" file).
* Miscellaneous
- The DOS and OS/2 platforms are no longer supported.
- Due to changes in the file data structure you will most likely
be asked whether to run the ERC when loading a board/schematic
pair created with an earlier version of EAGLE.
- Files from earlier versions of EAGLE may contain library objects
with the same names. This was caused by PASTE or ADD operations
with modified devices or packages. Version 4 no longer allows
this to happen, and therefore needs to make sure updated files
do not contain multiple objects with the same name. In order to
assure this, the update routine adds the '@' character and a
number to the names of such library objects.
- The library editor can now edit devices and symbols, even if the
user's license does not contain the schematic module.
- Avoiding multiple 'Save?' prompts for boards and schematics that
are connected via f/b annotation.
- When a file is modified while updating from a previous version
the resulting update report is now presented in a separate text
window.
Microstrip Patch Antenna Calculator. MPAC analyzes various parameters
including impedance and resonant frequency for a rectangular microstrip
patch antenna.
changes since last snapshot are (from the authors email)
verilog-20010407
--------------------
Still more progress on the new VVP simulation engine:
As with last week, this snapshot includes a lot of work on the ivl_target
API in support of code generation for vvp. Also, the vvp execution engine
has progressed some.
In fact, vvp has grown up to understand signed vectors and some signed
expressions. The signed vectors are mostly for VPI use, the signed
comparison instructions actually do signed work. Case comparisons are
new, along with %and and %or instructions, and %nor/r for reduction.
I also added a few new gate types to the .functor support.
A bug in the propagation of values by %set instructions has been fixed.
Specifically, the %set instruction not only sets the value of the .var
that it references, but also executes the propagation events that result.
This fixed some event ordering bugs.
Some VPI support needed by system.vpi is added to vvp to allow it to
properly handle signed signals, decimal values, and a few other details.
$display should work much better then it did last week.
Back in the vvp.tgt code generator, lots of new stuff is happening.
Several of the bitwise binary operators have been added, as well as
more comparison operators. This includes handling of signed expressions.
This also implies that vvp.tgt generates the proper .net vs .net/s
and .var vs .var/s statements.
User defined functions and tasks are now working. In fact, the vvp
target probably handles more functions (in behavioral code) then the
vvm engine. I've received several bug reports about user defined functions
with loops, that don't work under vvm. These should work with vvp.
Non-blocking assignments now work, too.
All forms of case/casex/casez are supported by the code generator, and
use the proper compare instructions. Forever, Repeat and While loops
also work now. A few bugs in event handling, and all the edge types
(including behavioral triggers) should work with limitations. Event or
is still in the works, and any-edge of large vectors (>4 bits) does not
work.
*Whew!*
As you can see, a *lot* of stuff is happening. I'm up to passing 110+
tests in the regression test suite (Icarus Verilog/vvm passes 318 tests)
so the changes are actually making things work. Test and be merry!
verilog-20010331
--------------------
More and more progress on VVP. More and more snapshots.
A lot of work has been done to the ivl_target loadable target API.
This API is growing to support the also growing tgt-vvp target. I've
added support for case statements, event triggers fork blocks.
Of course this also means that the tgt-vvp code generator and the
vvp simulator now support constructs including case, events, and
parallel blocks.
I've also fixed up the driver to properly report errors that tgt-vvp
detect. This makes the test suite regression script work a lot better.
I'm up to more then 70 tests in the test suite passing. I'm finding
that writing the code generator for vvp assembly is a *lot* easier
then writing a code generator for C++/vvm. Fortunately, the vvp
assembler is pretty fast.
At any rate, the vvp simulation engine is starting to show signs of
being useful. It still does not cover nearly as much of Verilog as
vvm, but what it does cover is so much faster that it may be worth
your while to try it out. And more eyes looking at it can only be a
good thing.
the authors announcement are:
There are a few bugs in the main compiler that are fixed. There has
also been an extension to the $fopen that adds support for opening
files for reading. The $fgetc has been added to take advantage of this.
This was done on the VPI side, although a slight extension to the mcd
functions was created.
The real news is the vvp simulation engine. I've added the tgt-vvp
code generator source and the vvp assembler/simulator, and the combination
actually produces the occasional working program. And it makes them
very quickly. So far as I can tell now, I am going to be very pleased
with the final outcome when this work is complete. However, it is not
at all ready to use. This snapshot is mostly to give a preview of things
to come to a wider audience.
HOW VVP WORKS
If you are accustomed to the existing vvm behavior, you remember that
the vvm simulator works by generating C++ and feeding that to the g++
compiler. Many of you are painfully aware of that.
VVP does *not* work like that. Instead of generating C++, the
generator emits assembly language for an abstract simulator processor.
The processor that the assembly targets doesn't really exist, but the
vvp program, included in this Icarus Verilog snapshot, assembles the
code to data structures in memory, then efficiently emulates the abstract
processor.
So the simulation of a program via vvp works by first compiling the
Verilog to vvp assembly. The vvp.tgt modules generates the code, and
is envoked when you use the ``-tvvp'' switch to iverilog.
The vvp assembly file so created is then passed to the vvp program to
be assembled and executed. There is a single vvp input file that is the
design to simulate. The vvp assembler is designed to execute the design
efficiently.
HOW TO LEARN MORE
The ivl_target.h header file describes the loadable target API that
the vvp code generator uses to gain access to the design. Then the
tgt-vvp directory contains the implementation of the vvp code generator.
The vvp directory contains the implementation of the assembler/simulator
that runs the compiled design. The README.txt file describes how the
vvp program works in general, and points to other txt files. There are
a variety of other .txt files in the vvp directory that describe how
the major components of the vvp program work.
first component is now a package name+version/pattern, no more
executable/patchname/whatnot.
While there, introduce BUILD_USES_MSGFMT as shorthand to pull in
devel/gettext unless /usr/bin/msgfmt exists (i.e. on post-1.5 -current).
Patch by Alistair Crooks <agc@netbsd.org>
QCad is a simple 2D CAD System. With QCad you can easily construct and
modify drawings with ISO-texts, dimensions, hatches and many other
features and save them as DXF-files. These DXF-files are the interface
to many CAD-systems such as AutoCAD and many others.
While here, update MASTER_SITE.
changes from last packaged version:
* Changes in Dinotrace 9.1b 2/13/2001
**** Documentation updates.
* Changes in Dinotrace 9.1a 1/22/2001
** Added analog waveform format. [Dave Colson]
Includes new Signal Waveform menu and signal_waveform command.
* Changes in Dinotrace 9.0m 11/21/2000
**** Fixed a bug reading compressed tempest on Digital UNIX. [Steve Hoover]
up a possibly out of date installed header from ${LOCALBASE}/include.
Note that while we don't support installing a pkg when a previous version
is installed, we should still be able to build it.
Problem noted in private email from Lennart Augustsson.
from the authors announcement:
So many things have changed since version 0.3 that there is no point
in listing them. There have been tons and tons of bug fixes and the
language coverage is better, and so on and so forth. It's just so very
much better then version 0.3:-)
speaking as a user, some of my personal favorites are:
- support for signed variables
- iverilog now gives correct return codes (which makes 'make' much happier)
for a more complete list, the commit messages for
pkgsrc/cad/verilog-current/Makefile contain the changes for each
development snapshot between verilog-0.3 and verilog-0.4
considered stable. Xcircuit now has the ability to pass parameters
to objects. For the moment, this only works with string parameters.
Integral parameters will be added in upcoming versions.
bug fixes and signed support (yay!).
detailed changes since last packaged snapshot from the
authors announcements:
Icarus Verilog snapshot 20010113
--------------------------------
We're getting close to release candidates. Maybe another snapshot, then
I start with making 0.4 release candidates. So lets get this tested so
that I can move forward!
This snapshot largely fixes a whole bunch of bugs. I'm working feverishly
to catch up to the reported bugs, but they are coming in about as fast
as I can resolve them. (Not that I'm complaining, mind you. These PRs
are really helping me make it better.) But that means I'm going to just
concentrate on getting as many PRs done as I can before the release.
The syntax of functions and tasks has been expanded to allow parameters.
This is not a common thing to do, but someone puts parameters if functions
The syntax of functions and tasks has been expanded to allow parameters.
This is not a common thing to do, but someone puts parameters if functions
so I had a PR to fix:-) Also I caught a problem with executing functions
that take no input parameters. In fact, a bunch of function related bugs
were fixed. I lost track of em all.
Ports of tasks weren't elaborated properly. I fixed this and a few related
problems so most legal l-values should work as task port expressions now.
Memories within tasks should also work properly now.
Speaking of ports, I now report errors when there is a port direction
for module ports that don't exist. In fact, there are a whole bunch of
cases where I've added required error messages.
The %d format of display strings now displays signed negative values as
negative values instead of the unsigned equivalent. This goes along with
the other signed arithmetic features from the -2000 standard that are now
supported.
I fixed up the Makefiles (thanks to a contribution) to support build using
the VPATH capabilities of the makefile. You should be able to compile for
multiple targets now from a shared source directory.
Icarus Verilog snapshot 20010106
--------------------------------
I'm just managing to barely keep up with the bug reports arriving in
the bug tracking system. I'm pleased with the success of the ivl-bugs
robot. These bug reports have allowed me to better manage and record
progress. Keep those bug reports coming!
I've added support for arrays of integer and time variables, as well
as the Verilog 2000 initialization syntax for these types. I have also
made some internal changes to integer support. Integers are now just
a shorthand for ``reg signed [31:0]'' and signed variable support has
made some internal changes to integer support. Integers are now just
a shorthand for ``reg signed [31:0]'' and signed variable support has
been generalized. This makes it easier on the code generators, as they
do not need to know that a variable was a integer, a time, a foo or a bar.
I few constant propagation errors have been fixed. Continuous assignments
of constants to nets should behave correctly now.
Many people noticed lack of expression support for parameters. In fact,
the problem was a lack of support for a bunch of specific operators. I've
added many operators. This has the side effect of improving constant
propagation as well, in some cases finding more dead code to eliminate.
This also affected expressions that were index expressions of memories
and vector declarations.
The / operator in continuous assignment expressions is fixed. There were
a few size related issue here that are now fixed.
I've added to the i3331364-notes.txt file a clarification of my position
on parse of repeat statements. This position is compatible with XL behavior.
Passing parameters to user defined functions in behavioral code was pretty
darn broken. I managed to fix this. You can tell that not many people use
user defined functions:-) (It doesn't help that Icarus Verilog is picky
about them.)
For vvm, I've put some effort into optimizing the compile time of programs
by reducing the size of the output code. I've reduced redundancies some,
and used loops to handle vectors where possible.
A few bugs related to $dumpvars were cleaned up. Function scopes work.
out of date - it was based on a.out OBJECT_FMT, and added entries in the
generated PLISTs to reflect the symlinks that ELF packages uses. It also
tried to be clever, and removed and recreated any symbolic links that were
created, which has resulted in some fun, especially with packages which
use dlopen(3) to load modules. Some recent changes to our ld.so to bring
it more into line with other Operating Systems also exposed some cracks.
+ Modify bsd.pkg.mk and its shared object handling, so that PLISTs now contain
the ELF symlinks.
+ Don't mess about with file system entries when handling shared objects in
bsd.pkg.mk, since it's likely that libtool and the BSD *.mk processing will
have got it right, and have a much better idea than we do.
+ Modify PLISTs to contain "ELF symlinks"
+ On a.out platforms, delete any "ELF symlinks" from the generated PLISTs
+ On ELF platforms, no extra processing needs to be done in bsd.pkg.mk
+ Modify print-PLIST target in bsd.pkg.mk to add dummy symlink entries on
a.out platforms
+ Update the documentation in Packages.txt
With many thanks to Thomas Klausner for keeping me honest with this.
Changes since the last packaged snapshot are (from the authors announcements):
Icarus Verilog snapshot 20001216
--------------------------------
This is the last snapshot before the holidays, so I hope it has your
favorite present in it. A lot of PR#s have been dealt with, and for a
brief moment I felt like I was getting ahead of the pending list:-)
I've added support for non-integer times, at least in a few contexts.
The `timescale directives should interact properly with the decimal
point in delays, causing more accurate timing simulations. This should
make vendor-supplied libraries work much better.
I've added support for signed reg variables. Signed expressions should
now generally do the right thing, but this feature needs much more testing,
and many more tests in the test suite. However, I do know that signed
comparisons should work properly. Bug reports for problems with signed
arithmetic are encouraged.
Many people have been having troubles with Cygwin compilation. The
problem was with the latest version of binutils. Venkat came up with a
solution that works with old and new binutils, so you can now compile
with the very latest cygwin software. This should make things a lot
easier for a lot of people.
I've made initial steps toward an HP/UX port. The configure script should
detect the right dl library to use, and the t-dll target should be able
to load loadable targets. I am looking for a volunteer to take responsibility
for the HP/UX port as I have no suitable machines. Said person should
be able to compile Icarus Verilog, manage HP/UX specific portability
issues, and be able to make precompiled packages when the stable release
is out.
I'm still looking for a similar volunteer for FreeBSD/{alpha,i386}.
Some more progress was made on support for PALs. I'm close to choosing
macrocell modes and configuring fuses. Won't be long now, folks.
Icarus Verilog snapshot 20001129
--------------------------------
few more constant propagation improvements this time, most notably
XOR an XNOR are now fairly complete. These are interesting as they are
generated by comparison operators so show up pretty often. And it is
common to compare numbers to constants. Thus, there are lots of oppor-
tunities for gate elimination!
Synthesis of unary ! now works. Unary ~| (reduction nor) should also
be in good shape now, as should binary || (logical or). Synthesis of
binary && is still a little shaky. Go ahead and file reports if you
trip on it. Binary != was broken with XNF synthesis, so that is also
fixed, along with a few cases of mangled XNF output. And there were
also a few bugs related to the CE of inferred DFFs, that didn't get
connected.
A *big* problem with synthesis occurred with non-blocking assignment.
Icarus Verilog simply failed to synthesize the r-value of the assignment
and all kinds of bad things happened. I fixed this, it's better now.
Whew! Lots of XNF synthesis bugs fixed! This is what happens when users
take the time to submit good bug reports.
There are also some bugs related to dead signal elimination that causes
Icarus Verilog to crash in some synthesis cases. These have been fixed
up so far as I know.
I have slightly improved root module detection of iverilog. If there is
only one module in a source file, it is pretty obvious that it is the root
module, even if it has ports. This is a common case for XNF synthesis
(especially when making small macros with Icarus Verilog) and should save
some typing and confusion.
-all previous netbsd patches have been incorporated (Thanks Steve!)
-changes from the authors announcement:
I fixed a problem with some systems not having getopt.h. I forget
which system it was, but configure takes care of it. I've also fixed
some broken install targets in the Makefiles.
I've added a new pin_count statement to PA files, so that the library
can provide to the user more information about the pinout of the device
in question. Applications may use this to help manage its pin binding
tasks.
A contributed 16l8 part description file was contributed, and included
in this release.
* A new part: wire jumper.
* Drag'n'drop from the part preview to place parts.
* A crude form of auto numbering when placing parts.
* Cleaned up makefiles and put some samples in
*<prefix>/share/oregano/samples/.
* Changed default spice executable name to spice3.
* Connection dots.
* A simple voltmeter function.
* Fix various ref/unref/sink design flaws, to
increased stability.
* Part browser remembers the previously selected part
when switching libraries.
* Should really work with libxml 2.x this time... :-)
* Reorganization of installation directories for model
and library files.
* The plot widget now features axis values.
* New parts: uA741 opamp and a simple zener diode.
* Parts and wires can be flipped horizontally and vertically.
* Enabled loading of simulation settings again.
* Added a simple text label item to put text on the sheet.
* Fixed the 'sometimes non-disappearing floating item' bug.
* Should now also work with libxml 2.x (untested).
* Switched C and B on the BJT transistor models.
* Removed the unfinished printing support for now.
* Redesign of lots of internals.
* Added lots of functionality to the parts library,
such as model files, and conditional values in templates.
* Improved a few of the icons.
* Fixed a bug where the name of the markers could not be edited.
* You can inspect the connection span, by holding Control while
moving the cursor over wires.
* Added the ability to rotate parts while placing them; press 'r'
to achieve this.
* Logging of Spice warnings and errors during simulation.
The messages can be shown in a log window.
* Beautification of the part browser UI.
* Added more tooltips and updated some translations.
* Fixed a few non-critical bugs.
* New and improved part properties editor.
* Improved user interface for the plot window.
* Internationalization fixes to netlist generation
and schematic loading/saving.
* The simulation now uses the user supplied time step size.
* French translation from David Monniaux.
* Even more refinement of the default library symbols/parts.
* Mission 'Code Cleaning' continues.
* Cut/copy/paste is implemented.
* The symbols are redrawn to look much nicer and more standard.
* Some new symbols, e.g. MOSFETs.
* There can be more than one part library, thanks to Elker Cavina.
* A bug with simulation time settings was fixed.
* There is a problem with some spice packages, that make them generate
binary output, even though the default should be ascii. This is now
fixed by telling spice to always output text.
* The help files are now installed in the rpm package.
* Lots of code restructuring and cleaning.
changes since the last packaged version (from the authors announcements):
Icarus Verilog snapshot 20001119
--------------------------------
The big change here (code wise) is improved and corrected constant
propagation. I was missing OR, NOR, NAND and XOR propagations, and
got some of the AND calculations wrong. This fixes this shortcoming
and in some cases this actually may speed up your compile a tiny bit.
Some more dangling signals are also eliminated.
supply nets are now working (PR#17). They also will trigger constant
propagation (as they have constant values) in certain cases.
Those of you doing cygwin compiles have trouble compiling parse.cc. I've
put into the cygwin.txt some slightly better instructions for dealing with
this situation, when it comes up.
I've also added missing symbols to ivl.def, so that tgt-stub properly
links.
Icarus Verilog snapshot 20001112
--------------------------------
This snapshot includes support for MOS et al devices as contributed
by Tim Leight. It appears to actually work as advertised, and I also
have from him a collection of tests that I'll be adding to the test
suite as soon as I get copyright information from him. So if you have
been dreaming of simulating MOS devices with Icarus Verilog, give this
a try. This update also fixed PR#27.
I've also cleared up a few bugs related to unconnected module ports.
Module port syntax is pretty byzantine, as PR#38 shows.
The loadable target API has gained access to flip-flops. This is required
for PLD code generation to work. I think the ivl_target API now supports
the minimum devices needed to generate PLD files, and I'm on to the task
of getting ancillary PAL support working.
Icarus Verilog snapshot 20001104
--------------------------------
Yes, I've managed to find the right bits to get Icarus Verilog to compile
on RedHat 7.0, and this snapshot includes those fixes. It took some back-
and-forth with tech support at RedHat to get it going.
I've also fixed up make check so that it works in general. If you use
"make check" after building, the makefile will run the examples/hello.vl
program through the local parts to make sure they minimally work.
I've added support for the "time" data time and more complete support
for the $time system function. These should work properly in all cases
now, so cases of not working are worthy of a bug report.
I've also integrated a re-implementation of sequential UDPs from Stephan
Boettcher, so I would appreciate it if all you folks using primitives
give this a fresh test. (It should be an improvement.)
This is a relatively small message, which doesn't reflect the complexity
of the changes. The "time" support in particular caused a lot of threads
to be pulled. Also, I've been doing some PLD stuff on the side, so I've
been busy.
I've also knocked of PR#11, 14, 33, 34, 39 and a few other bugs.
changes (from the announcement):
The libipal library has gained access to more structural information
about the device, including enable SOPs. It is also now possible to
lookup a SOP by name and by pin. Also, access to sop fuse positions
has been improved.
The toplevel makefiles were changed to use $(MAKE) instead of make.
There are a few other niggling makefile fixes as well.
ipalrev and ipaledit now both take the -p flag allowing you to choose
the architecture for your device, and there are now two devices to
choose from. (both 22v10s:-)
ipalrev was seriously confused about inversions and the sense of things,
but that should be all cleared up now. It does a decent, if not complete,
job of decompiling 22v10 designs.
And finally, the PA file format has been extended to accommodate the
new library features, and PA files are now named according to a naming
convention for identifying devices.
from the NEWS file:
New in 20001123:
- Saving wave and panel configuration as guile scripts.
- Executing guile scripts from menu or command line (-s <script> option)
- Remote control using the gwave-exec and gwaverepl utilities
New in 20001004:
- Spice3/Ngspice rawfile improvements: binary files now work!
- Other minor file-reading improvements.
- spice source code to examples for which I could still find it.
New in 20001004:
- Major improvements to handling of binary files produced by HSPICE.
- Overhaul of input of spice3/ngspice raw files; more robust and tolerant
of complex numbers.
- User interface improvements: tooltips added. User's .gwaverc no longer
required to do lots of standard setup. system.gwaverc can be copied
to $HOME/.gwaverc and edited to taste.
- sp2sp utility included for converting any spice file readable by gwave into
a convenient tabular ascii format.
from the history file:
----------------------
New features:
1. New probes: diode G, mos IBD, IBS, GBD, GBS.
2. New options: "floor" and "vfloor". (Floor was in the manual, but
not in the simulator.)
Improvements, bug fixes, etc.
1. There is a change to the way behavioral modeling conditionals are
handled. It should now be 100% compatible with SPICE, considering the
subset that duplicates SPICE. There are still significant extensions
beyond SPICE, particularly that you can have behavioral resistors,
capacitors, inductors, etc.
2. Parameter default calculations are now done in a manner consistent
with Spice 3f5. Previously, it was supposedly consistent with Spice
2g6.
3. A bug in calculation of threshold voltage of the level 6 model, for
P channel devices, has been fixed.
4. A bug in calculation of Meyer capacitances when the device is
reversed has been fixed. This bug sometimes caused a discontinuity at
vds=0.
5. I have added some smoothing to the Meyer mos capacitor models.
This improves convergence. The down side is that sometimes the
answers are different. It is probably a little better, when
considering closeness to reality, but it is still Meyer's model.
6. MOSFET parasitic diodes are now the same as those used in Spice.
7. There are subtle changes in the diode model. I think this usually
improves convergence.
8. Charge calculation in Meyer capacitors and diode capacitiors is now
supposedly Spice 3 compatible.
9. An error in BSIM3 scaling has been fixed.
Some things that are still partially implemented:
1. Internal element: non-quasi-static poly-capacitor.
2. BSIM models, charge effects.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. The makefile does not set up the proper link for the model
compiler. You need to do it manually.
3. A bad setting of "vmax" and "vmin" can lead to convergence to a
nonsense result. It is not as bad now as it used to be.
note, this is the development snapshot version of the package. As stable
releases become available, there will be a ipal package.
from DESCR:
Icarus PAL is a set of libraries and utilities for manipulating PAL
designs. The design information is conveyed in the industry standard
JEDEC file format.
Icarus PAL accepts parts descriptions that detail the device
structure, capabilities and pinouts so that software can be written to
work relatively independent of the part type. These parts descriptions
also describe how the fuses of a device are arranged, so that
synthesis tools can generate fuse maps to get the desired
functionality and pinout. See as a commented example the description
in the pa/pal22v10.pa description.
The ipaledit program takes as input a .JED file and displays the PAL
design. It shows the sum-of-products as a fuse matrix, and shows the
macrocell configurations in convenient form.
The ipalrev program takes as input a .JED file and reverse compiles
it, producing a Verilog program that logically describes the
design. This use useful for moving old designs to new tools.
Please note that this package is a development snapshot and while it contains
the latest and greatest features, it may be buggy as well. When
available there will be a seperate ipal package which will be made of
the stable releases.
from DESCR:
The program is a viewer and editor for:
-GDSII files, KEY files (own made extended GDSII in ascii format) and
DAVID MANN files (flash format for mask plotting)
Features:
-It allows to draw primitives on a chosen layer, and to manipulate them.
-stack oriented tools allows zooming while drawing new primitives and
editing them. This also makes it possible to draw extremely accurate.
-primitives on the layers or/can be transparent colors and fill patterns
can be set on a layer basis
-drawing order of layers can be changed
-a hiearchy of pictures, named structures, can be handled and manipulated
-saving as a bitmap and other formats.
-measuring distances
-adding user defined properties to primitives
-boolean OR AND EXOR A-B B-A
-positive and negative process offset
-circle recognition in polygon and polyline data.
-move copy delete etc.
-transformations (scaling , rotation , moving)
-flatten the hiearchy of the drawing
-drivers for CNC (laser and milling machinery)
NG-SPICE is the program being developed as the replacement for Berkeley
SPICE. Using the Berkeley code as a starting point, the NG-SPICE team
is working on improving the build system, adding to the models, and
improving the analysis capability.
SPICE is a general-purpose circuit simulation program for nonlinear dc,
nonlinear transient, and linear ac analyses. Circuits may contain resistors,
capacitors, inductors, mutual inductors, independent voltage and current
sources, four types of dependent sources, lossless and lossy transmission
lines (two separate implementations), switches, uniform distributed RC
lines, and the five most common semiconductor devices: diodes, BJTs, JFETs,
MESFETs, and MOSFETs.
The program xcircuit is a generic drawing program tailored especially
for making publication-quality renderings of circuit diagrams (hence
the name). The output is pure PostScript, and the graphical interface
attempts to maintain as much consistency as possible between the X11
window rendering and the final printer output.
xcircuit is mouse, menu, and keyboard-driven, with the emphasis on
single-character keyboard macros.
Package provided by Jason Beegan <jasontd@indigo.ie> in PR 11383 with
some minor modifications by me.
from the authors announcement:
-----------------------------
The loadable target module API is starting to take shape.
That is the major thrust nowadays with Icarus Verilog, after all, so
progress is being made here. The biggest change is in fact a philosophy
change. The target module now needs only a single symbol -- target_design --
to receive the whole design. The target module can from there and using
the API access the entire design randomly. So if you wanted to implement
a graphical browser, you could:-)
I've added support for the l-values of procedural assignments, and also
back pointers to objects that reference ivl_nexus_t objects. This closes
the loop so that there should be no dead-ends in the design.
I've clarified and expanded the descriptions in the ivl_target.h header
file. There should be just about enough documentation to properly used
all the various types. (Have any of you tried to write GIMP plug-ins?
Have you looked at the libgimp header files? Have you seen any comments
there?-( I won't ever sink to that level, I hope.)
I've also imtegrated updates to the Cygwin32 port to support loadable
targets under Cygwin32. After much struggling, Venkat managed to discover
the secret magic needed to get load time symbol binding to work. Hopefully
I didn't break it too bad when I changed the API again. (I think it is
still fine.)
as files instead of requiring the user to install one of our largest packages
just to build them. Note, in the previous version of this pkg, the docs generated
with latex weren't even being installed (!).
Notable changes since the last pkged version are:
Gwave NEWS --- history of user-visible changes. -*- text -*-
New in 20000518:
- Logarithmic scales working on both X and Y axis.
New in 20000509:
- First public guile/guile-gtk release.
- Popup menu on visible-wave button can activate per-waveform dialog box
- Logarithmic scale on Y axis working; on X axis it isn't quite there yet.
New in 20000108:
- Merged in guile and guile-gtk; the GUI is mostly written in guile now.
- Some additional improvements to reading of HSPICE input. Reading partial
files from simulations still in progress works for ascii .tr0 files.
Changes included in version 2.0.4
---------------------------------
- Fixed printing under windows.
- You can now plot the real and imaginary parts of the
circuit input and output impedances
Changes included in version 2.0.3
---------------------------------
- Moved to Qt version 2.1.0
- The help browser is now integrated into the ViPEC application.
- Fixed a bug in calculating the circuit output impedance.
- Input and output impedances ouput to a graph now works.
Changes included in version 2.0.2
---------------------------------
- Improved data storage of graphs and Smith charts
- Double buffering implemented for drawing of graphs
and Smith charts to reduce flicker.
- Improved font management
- Fixed display bug in Table view
- Fixed bug with output to 2 port parameter files under Windows
- Added support for Group Delay, see help files for more details
as well as sample circuit: group_delay.ckt
ACS 0.27 release notes (06/03/2000)
New features:
1. BSIM3 model, DC.
They work for AC and transient analysis, but only the DC effects
actually work. The next release should have the charge effects. For
now, it fakes it with Meyer's model.
2. A first cut at a model compiler, to aid in development of new
models. Models are described in a ".model" file, which is processed
to automatically generate the ".h" and ".cc" files. This version
fully handles the ".model" statement part of it, but leaves the device
and common sections the old way. Eventually, the entire process will
be automated. The old way still works.
3. "Fit" behavioral modeling function, which fits a curve to a set of
data. You can specify the order of the fit, which is piecewise
polynomials. For now, the order may be 1 (linear, like PWL) or 3
(cubic splines). You may also specify the boundary consitions.
4. More probes.
Some things that are partially implemented:
1. Internal element: non-quasi-static poly-capacitor. It is needed by
the BSIM3 and EKV models. Eventually, it will be available as a
netlist item, but not yet.
Bug fixes:
1. PWL could fail if there were duplicate points at the beginning. It
still does, but gives a reasonable error message.
2. Some "dot commands" were ignored if there were spaces before the
dot. This was particularly annoying if the line was supposed to be
".end" which should make it exit. It didn't, leaving it in
interactive mode, a major annoyance in a script.
Other improvements:
1. There is a change to the way integration in capacitors is done. It
is now strictly based on charge (i = dq/dt). The old version was
based on capacitance (i = C * dv/dt) which is strictly incorrect. The
dC/dt term was missing (i = C * dv/dt + v * dC/dt). This is a
non-issue when C is constant.
2. More documentation on internals.
Changes that I think are improvements, but some may disagree:
1. The command line is a little different. In the old version,
"acs file" would run it, and whether it exited or not depended on
whether there was an ".end" line. Now, by default, it just loads the
file in preparation for interactive use. If you want batch mode, say
"acs -b file".
2. The regression suite is included in the standard distribution.
Changes that are not really improvements:
1. Due to the model compiler, the build process is a little more
complicated. To do a complete build, you must build the model
compiler first, then the simulator. If you are not making any new
models, you can probably get away with just building the simulator.
This will change in a future release.
Bugs:
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. The makefile does not set up the proper link for the model
compiler. You need to do it manually.
Hot items for a future release (no promises, but highly probable):
1. Charge effects in BSIM models. They are computed, but not loaded
to the matrix.
2. Completion of model compiler, and its documentation.
3. Completion of multi-rate.
4. Homotopy methods to improve convergence.
5. Transmission line accuracy and speed improvements, using a step
control mechanism similar to that used for capacitors.
6. Parameterized subcircuits and defined parameters.
7. A "trigger" element, so time dependent values can be triggered by
the circuit, as an alternate to simple time.
To reach me, try this email address:
aldavis@ieee.org
ACS ftp sites:
ftp://ftp.geda.seul.org/pub/geda/dist/acs-0.27.tar.gz
http://www.geda.seul.org/dist/acs-0.27.tar.gz
ftp://sunsite.unc.edu/pub/Linux/apps/circuits/acs-0.27.tar.gz
