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5 commits

Author SHA1 Message Date
drochner
4565c457e6 update MyHDL to 0.5.1 
There is no usable changelog; I've found one real bug closed in the
tracker: A verilog '>>>' is generated as appropriate for signed numbers.
 2006-05-04 16:58:05 +00:00
drochner
4ca0722c59 update to 0.5 
major changes:
-supports Python decorator syntax for generators (needs 2.4)
-intbv() doesn't have a default anymore
-many improvements to Verilog conversion
 2006-02-10 16:06:46 +00:00
agc
7ea6ce3da9 Add RMD160 digests in addition to SHA1 ones. 2005-02-23 14:59:23 +00:00
drochner
154f18aa7d update to 0.4.1 
changes:
* VCD output for waveform viewing
- function additions
- needs Python 2.3, 2.4 is OK
* Conversion to Verilog to provide a path to implementation
* Added cosimulation support for the cver Verilog simulator.
- bugfixes
 2005-01-05 15:20:10 +00:00
drochner
dfe2fe099e a library which uses Python as a hardware description language, using 
the new generator constructs (like pysim, at a first glance)
 2003-06-05 18:50:54 +00:00