Problems found with existing digests:
Package suse131_libSDL
1c4d17a53bece6243cb3e6dd11c36d50f851a4f4 [recorded]
da39a3ee5e6b4b0d3255bfef95601890afd80709 [calculated]
Package suse131_libdbus
de99fcfa8e2c7ced28caf38c24d217d6037aaa56 [recorded]
da39a3ee5e6b4b0d3255bfef95601890afd80709 [calculated]
Package suse131_qt4
94daff738912c96ed8878ce1a131cd49fb379206 [recorded]
886206018431aee9f8a01e1fb7e46973e8dca9d9 [calculated]
Problems found locating distfiles for atari800, compat12, compat 13,
compat14, compat15, compat20, compat30, compat40, compat50,
compat50-x11, compat51, compat51-x11, compat60, compat61,
compat61-x11, fmsx, osf1_lib, vice, xbeeb, xm7.
Otherwise, existing SHA1 digests verified and found to be the same on
the machine holding the existing distfiles (morden). All existing
SHA1 digests retained for now as an audit trail.
Changes since previous version:
#00061 michael pp Michael Dales (michael@dcs.gla.ac.uk) Thu Sep 27 10:41:39 BST 2001
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* Contains lots of code by Hanish Menon [www.hanishkvc.com] to enable uCLinux to
work on SWARM.
* Updated the logic in armproc.cpp wrt UART and LCD Ctrls so that
they can rise interrupts to the Interrupt Ctrl if required.
* Updated certain messages and return values.
* Added the srec loader
* Updated the LCD controller address
* ReIntroduced the Parse_Opts logic.
* Will be adding support for SREC file loading.
* Fixed a problem in the bin/Makefile
* Added support for a minimal UART controller.
* Updated the earlier sample LCD controller which I had written wrt its Addr.
* Looking into SWARM and the Device/Pheriperal interface logic in SWARM
* Added a partial LCD Ctrl logic to test the interface logic
* fix a problem with ldms
#00060 michael pp Michael Dales (michael@dcs.gla.ac.uk) Tue May 15 22:53:15 BST 2001
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Added cache invalivation functions to the system coprocessor.
#00059 michael pp Michael Dales (michael@dcs.gla.ac.uk) Fri May 11 16:52:45 BST 2001
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Corrected the n-way set associative cache. Added functionality to the system
co-processor to allow me to read the cycle counter, cache hit counter, and
cache miss counter in an application, using register 11 with opcode 2 set to
0, 1, and 2 respectively.
#00058 michael pp Michael Dales (michael@dcs.gla.ac.uk) Thu May 10 14:05:25 BST 2001
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Added a n-way set associative cache. Default is now 8k 4-way shared cache.
