changes from the last packaged snapshot (from the authors announcement):
---------------Icarus Verilog 20000506 Snapshot------------------
A lot of internal reworking has been done on this, so there might be
problems with things like symbol binding. But I think this is much better
then the last snapshot. I am once again starting to think about a
stable release. I'll shoot for the end of May, so if there is anything
you want to see in that release, start pestering me.
The big job has been a rewrite of the symbol table that holds signals.
The previous elaboration and lookup code for signals/memories did not
work properly when hierarchical names were used in the context of tasks
and functions. Also, the old table kept all the signals is a single
lookup table that failed to take advantage of knowledge of the current
scope.
All that is changed. signals are now elaborated after parameters and
before processes, so all hierarchical accesses should work properly now,
no matter how contorted. I've also fixed some bugs with function/task
parameter passing.
I've also added some infrastructure for supporting system functions, and
I've added an implementation of the $random system function. This currently
uses the native random(3) C library function, but once I get access to the
standardized algorithm, I'll implement that.
There are also a few fixes to elaboration of ternary operators. They were
a bit touchy about result bit widths.
A few preprocessor bugs have been fixed, especially related to the
`ifdef/`endif tokens. People are all the sudden starting to use the
Icarus Verilog preprocessor, so some long-standing bugs have been caught.
The iverilog command had a few path problems fixed, and the remaining
necessary switches have been added. I really encourage people to start
using iverilog in place of verilog. The test suite now uses iverilog to
run the compiler, so should you. There is a man page.
The many bug fixes and changes since the last packaged snapshot
are (from the authors announcements):
Icarus Verilog 20000428 Snapshot
--------------------------------
This one clears up some pretty nasty and subtle bugs. If you've been
sending me bug reports, you're probably turning blue holding your breath
in anticipation of this snapshot. Breath in, Breath out.
Hooray, both force and release work properly. I'm happy about that,
release worked out a bit easier then I expected. These should be useful
to test bench designers.
The big news this past week, however, has been bug fixes. Lots of bug
fixes. I got lots of bug reports and I killed pretty nearly all of
them. There were lots of nasty icky problems with passing parameters
to/from tasks, especially when memory words were involved. I fixed up
a whole bunch of these, and now parameter passing should work pretty
will, modulus the few remaining bugs I'm not seeing yet.
The iverilog command is in better shape now, and I encourage people
to use it in place of the older "verilog" driver script. There is a
man page for iverilog, and it supports all the switches needed to do
simulation and synthesis. I would like people to start getting this
driver well tested and the bugs worked out, because it is going to be
the main driver come the next stable release.
Some neat new XNF features are happening. I synthesize identity compare
in XNF, and a few other missing operators. But the really neato part is
that I've taught Icarus Verilog to generate PIN records for module
ports, so that you can make XNF macros out of Verilog source. If you
elaborate a module that has ports, the XNF code generator will automatically
generate the necessary symbols so that external XNF tools can link the
generated output into larger designs. I've compared the XNF files from
Icarus Verilog with those generated by Abel, and they appear the same
to my eyes.
Icarus Verilog 20000421 Snapshot
--------------------------------
Bunches of bug fixes, and a few new features come with this snapshot.
This snapshot makes headway in both simulation and synthesis. I'm
also starting to make a big dent in my todo list for the 0.3 release.
The bunches of little bug fixes in this snapshot are a direct result of
bunches of bug reports this past week that I was able to deal with. If
you've been reporting bugs, this may contain your fix.
I redesigned the process implementation in the vvm backend, so the generated
code is a bit cleaner, and threads are lighter weight. And while I was at
it, fork/join now should work properly. I know there were a bunch of you
out there asking for this, so here it is.
I've incorporated into this release improved runtime support for integer
multiplication, it should now work now matter how incredibly enormous
you make the operands. Thanks to Chris Lattner for contributing the generic
multiply.
I've improved synthesis somewhat, there were some expressions in some
contexts that were not getting synthesized by the -Fsynth functor. This
is fixed, and I'm also starting to add some XNF specific optimizations
into the -Fxnfio functor. I do sensible things with identity compare,
for example.
I've added the program ``iverilog'' to be a new driver program written
in C instead of as a shell script. This driver supports the -tnull,
-txnf and -tvvm targets, as well as the -E flag that causes only the
preprocessor to be run. This should be interesting to those of you who
are looking for a working preprocessor. I'm still working on the -D and
the -I flags, but I expect this program to replace the verilog.sh script
before the 0.3 release.
Icarus Verilog 20000414 Snapshot
--------------------------------
All event handling is now complete. Yet another subject is behind me, and
on I go. By complete, I mean that named events, edge triggers, wait, and
lists of events all work. This took a little longer then I expected, so
some of the other things I wanted to work on had to wait.
As a side effect of event and thread scheduling work, I changed the way
that threads are generated in vvm. The result is that threads should be
a little faster at run time, and a lot faster at compile time. A *LOT*
faster at compile time. (Apparently, Verilog XL is still considerably
faster, but hey, I'm working on it.)
changes since the last packaged snapshot include:
Icarus Verilog 20000326 Snapshot:
--------------------------------
The VVM backend rewrite continues. More templates are gone, and the
bit functions have been pretty much rewritten. The vvm library now handles
bit values with strengths, and most of the devices to the right things
with those strengths.
The most obvious implication of this is that you can write multiple
drivers to a net and expect the values to be properly resolved, and in
particular the HiZ value works as it should. So I am well on the way to
completing strength modeling support.
What is still missing is support for strength specifications in the
Verilog source. Although the parser supports the strength related keywords,
they are not passed on to elaboration, or used to generate drivers with
the proper strengths. So that's in the works.
While doing all this VVM rewrite, I've made the generated code considerably
smaller. And of course fewer templates are used. The upshot of this is that
compiles of larger designs should go a whole lot faster. This is important
because people are using Icarus Verilog for increasingly larger designs.
On some larger examples, I've achieved more then 3X compile time improvement.
Icarus Verilog 20000409 Snapshot:
--------------------------------
Named events now work! Event object declarations and trigger statements
are fully supported, and blocking on a single event also works. I'm not
up to named events in event lists because I'm in the midst of redesigning
the way events on nets and regs are implemented. However, the common case
works fine, so there you are.
I've also added support for some more arithmetic operators. Division and
Modulus now work in many contexts, and are not far from working everywhere.
Also, comparison operators work in places they used to not.
There was a compile error in memory objects that managed to slip through
a couple snapshots, that I finally cured. The problem was pretty gross,
but somehow not quite tickled by my tests. Oh well.
I've integrated some VCD improvements from Anthony Bybell. Some of you
recognize the name as the author of GTKWave, so if he says VCD works like
so, then that's how VCD works:-) Anyhow, he fixed the VCD output to be
more portable, and also a bit smaller when vectors are involved. He also
fixed some bugs with multiple calls to $dumpvars.
- Make sure -Rpath is done correctly
- Make sure qt libs are found
- Make sure -lz -lpng -lSM are included as libqt needs functions
from these libraries.
components. This allows users of Qt to specify QTDIR=/path/to/qt instead
of having to patch all configure scripts and makefiles to look for alternate
names. This is the recommended approach from Troll Tech (Qt authors).
update pkgs which use qt1 to reflect this.
New features:
1. BSIM1, BSIM2 models -- DC only.
2. New elements:
trans-capacitor
voltage controlled capacitor
voltage controlled conductance
voltage controlled resistor
3. Optional new syntax, with type first so component labels can start
with any letter, and the choice of components is no longer limited by
the 26 letters. This was necessary for a clean syntax
for #2.
4. Some new parameters on existing devices, also a side
effect of the BSIM work.
5. The manual in HTML form. The manual source is still in LaTeX,
which can be used to generate HTML, PDF, Postscript, or many other
formats.
Bug fixes:
1. An error causing truncation error to be underestimated has been fixed.
Other improvements:
1. MOSFET model evaluation is a little faster, due to use of one of
the new elements to replace several old ones. I have seen 40%, but
20% is more likely. The improvement is most evident on busy circuits,
where the ACS speed enhancements based on latency exploitation
contribute more overhead than their value, that is .. the type of
circuit that has run faster in Spice than ACS.
2. More documentation on internals.
Changes that I think are improvements, but some may disagree:
1. Truncation error based step control is disabled when Euler's method
is selected. The justification for this is that the reason for
selecting Euler's method is to avoid the artifacts of high order
methods on "stiff" poles. Without this change, a "stiff" pole would
cause an unreasonably small step size. This did not appear to be much
of a problem in the old release because the use of an incorrect
formula for estimating truncation error. A "stiff" pole is one that
has a response so fast it can be thought of as instantaneous.
2. The "help" command, with its 4 year old help file, has been
removed. The concept is really obsolete. With the HTML form of the
manual, a full online manual is a better replacement.
Notable changes since the last pkg are (from the snapshot announcement):
Parameters are complete.
What this means is that I finally got around to supporting defparam,
and while I was at it I rewrote the entire parameter handling and added
the parameter support included in 1364-2000.
I have rewritten major portions of the VVM backend. The vvm_nexus class
has been introduced to the fray, and all the device implementations in
the VVM library now use the nexus to drive and receive values. An advantage
of this scheme is that the t-vvm backend code (in ivl proper) is simpler,
and so is the generated C++ code.
I also removed most of the template classes. This proved to be a huge
compile-time benefit (though compiling twice as fast really only matters
for large programs) and it doesn't seem likely to hurt run-time performance.
A few remain, either because they seemed harmless (the N-wide logic gates)
or I couldn't yet figure out a good way to replace them (vvm_bitset_t).
A side benefit of this is that the vvm library may now be a modeling
library that ordinary humans can use to write their models in C++. This
may provide the unexpected benefit of heading me towards incremental
compilation of designs. So who was it who was beating me over the head
asking for that?-)
I also fixed a few minor problems with the preprocessor. Those of you
who reported problems with `includes and `defines should check this out.
Dinotrace is a tool designed to aid in viewing Verilog Value Change
Dump (.vcd), ASCII, Verilator, Tempest CCLI, COSMOS, Chango and Decsim
Binary simulation traces. It is optimized for rapid design debugging using
X-Windows Mosaic.
verilog-current pkg to track development snapshots.
This version has minor bug fixes over the previous snapshot package. Notable
$display of a memory element now works correctly and a bug in $readmemb has
been fixed.
Gwave is a viewer for spice-like simulator output and other analog data
Gwave can read several file formats. It attempts to guess file formats
based on filename, and then tries all file formats until one succedes.
These file formats are known:
CAzM transient output (*.[BNW])
HSPICE binary and ascii formats (*.tr0, *.sw0, *.ac0)
Spice2 and Spice3 "raw" output (*.raw)
An ascii format with whitespace-seperated columns and column headings,
such as that produced by ACS (Al's circuit simulator). (*.acs, *.asc, *.ascii)
The "Export Postscript" and "Export PNM" options on the main File menu
provide the rudiments of output for inclusion in other
documentation. They and simply write out files called gwave_out.ps and
gwave_out.pnm into the current directory. In the future, a dialog box
will allow configuring the print and export output.
Changes include:
* New dialog boxes by Matt Ettus:
- A much improved attribute edit dialog box
- A multiple attribute edit dialog box
* Improved Hierarchy Support:
- Hierarchy/Down Schematic
- Hierarchy/Down Symbol
- Hierarchy/Up
* Text alignment.
* Attributes are now required to have no spaces besides
the equals sign on each side. This shouldn't cause
any problems for anybody.
* Bunch of updates to the various gnetlist backends
(basically all submitted changes have been integrated).
Integration of JM Routoure's PCB backend work (Thanks!).
Bug fixes and improvements by Matt Ettus, Stefan
Petersen and Bas Gieltjes.
* Added a bunch of contributed symbols. Thanks to
all that have contributed! There are now 566 symbols
in the library.
* Documentation. There are the beginnings of docs now.
Here's the current list:
attributes.txt -- Master attribute list
fileformats.html -- gEDA file formats
gschem.txt -- The start of a serious user's
guide keymapping.html -- Stefan's keymapping
document netattrib.txt -- A HOWTO on the net=
attribute symbols.html -- The ever useful symbol
creation guide
* Bug fixes and improvements to some of the utils.
* Lots and lots of bug fixes (and bug introductions).
Cascade is a program for analyzing the noise and distortion
performance of a cascade of elements in an electronic system. A
typical application of cascade is the analysis of a receiver. A text
description of the receiver block diagram consisting of things like
amplifiers, mixers, and filters is entered into cascade. Each element
is characterized by its gain and optionally noise figure, and third
order intercept point. The program then analyzes the system and
produces a report detailing the performance at each stage.
A summary is produced which shows the relative contributions to the
total system performance of each block. This allows easy
identification of what limits system performance.
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
compiler, compiling source code writen in Verilog (IEEE-1364) into some target
format. For batch simulation, the compiler can generate C++ code that is
compiled and linked with a run time library (called "vvm") then executed as
a command to run the simulation. For synthesis, the compiler generates
netlists in the desired format.
The compiler proper is intended to parse and elaborate design descriptions
written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
complex standard, so it will take some time for it to get there, but that's
the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
and some -1999 features will creep in.
ACS is a general purpose circuit simulator. It performs nonlinear
dc and transient analyses, fourier analysis, and ac analysis
linearized at an operating point. It is fully interactive and
command driven. It can also be run in batch mode or as a server.
The output is produced as it simulates. Spice compatible models
for the MOSFET (level 1,2,3,6) and diode are included in this
release.
Since it is fully interactive, it is possible to make changes and
re-simulate quickly. The interactive design makes it well suited
to the typical iterative design process used it optimizing a circuit
design. It is also well suited to undergraduate teaching where
Spice in batch mode can be quite intimidating. This version, while
still officially in beta test, should be stable enough for basic
undergraduate teaching and courses in MOS design, but not for
bipolar design.
In batch mode it is mostly Spice compatible, so it is often possible
to use the same file for both ACS and Spice.
enhancements. Most notably, gEDA was split into several independent
modules, using a common library 'libgeda'. These modules are now separate
packages with geda now becoming a meta package.
