date. While here bl3ify. Changes are:
Covered-Related NEWS
====================
* 04/11/2004
Release covered-20040210 made. A lot of work has gone into this release to make the report
output more readable and concise. Several bug fixes have been made as well. A GUI is on
the way for report viewing that will be available in alpha version in the next development
release. Below are some of the highlights of this release.
- Added GUI interfacing functions in preparation of upcoming GUI report viewing utility.
- Added more information about expressions to line and combinational logic coverage verbose
information. Rather than just outputting the RHS of the expression, the LHS and assignment
operator (blocking or non-blocking) or IF statement are output to give the user a better
context of the missed logic.
- Fixed bug in param.c where parameters found in the RHS of expressions that were part of
statements being removed were not being properly removed.
- Fixed bug in sim.c where expressions in tree above conditional operator were not being
evaluated if conditional expression was not at the top of tree.
- Changed output of logic in combinational logic verbose coverage reporting to (by default)
use the same format (in terms of endline characters) as the logic was found in the source
code.
- Added '-w [<line_width>]' option to report command that causes combinational logic to be
output to report as much logic as will fit in the value of <line_width> in the report. A
default value of line width is specified internally in Covered to be 105 characters;
however, the user may make this value larger or smaller to suit. This value reverses the
effect of the above bulletin. Added this option to Covered's regression suite to test.
- Completely modified output format of missing combinational logic coverage. Removed a lot
of coverage information that was extraneous. When three or more subexpressions are ANDed,
ORed, logical ANDed, or logical ORed, coverage information is output in a special way to
increase readability/understandability for this coverage.
- Added "GENERAL INFORMATION" section to all reports which specifies general information
about this report (this eliminates a lot of redundant information in the report to improve
readability).
- Added the name of the CDD file from which a report has been generated from in the
GENERAL INFORMATION section of the report.
- When a CDD file is created due to merging CDD files, the names of the original CDD files
are now stored in the merged CDD file. This information is output in the GENERAL
INFORMATION section of the report (created from this merged CDD file) to indicate to the
user this information.
- If a CDD file is created due to merging CDD files and the leading hierarchies in each of
those CDD files are different, a bullet in the GENERAL INFORMATION specifies this and
reminds the user that the leading hierarchy information will not be output in the rest of
the report (instead the string "<NA>" replaces the leading hierarchy information). This
will help to eliminate confusion when viewing the reports and fixes an outstanding bug
in Covered.
- Added starting and ending line information to module structure for GUI purposes.
- Removed scope information in CDD file for expressions, signals and statements. This
information was not used, caused CDD files to become excessive in size and mildly speeds
up reading in CDD files.
- Fixed bugs in combinational logic report section where summary coverage numbers and verbose
coverage numbers did not agree.
- Removed 'c' directory in 'diags' directory and cleaned up Makefile to run regressions.
- Masked off the value of the SET bit in expressions output to CDD files. This information
is not needed and sometimes caused regression failures due to CDD file mismatches on
different platforms or using different simulators.
- Modified regression Makefile to specify the 'vvp' command prior to the compiled VVP
executable when running Icarus Verilog regressions (due to recent change to IV).
- Changed instance-based reports to not merge child instance coverage information into parent
instance coverage information. This is not done in module-based reports, makes reading
this information confusing and doesn't provide us any extra information.
- Fixed bug where modules were being reported in verbose reports when coverage numbers were
100% covered.
- Changed toggle coverage report output to output toggle information in hexidecimal format
versus binary format. This keeps the toggle coverage information more succinct/readable.
Added underlines between every 4th hexidecimal value to help user's to discern the bit
position of a toggle bit.
- Changed the format of the report entirely to enhance readability (many changes here that
the user will immediately see).
- Updated user documentation for new changes and added new section called "Reading the
Report" which will walk the user through several reports and how to interpret the report
information. This section is still in progress at this time.
- Updates to development documentation.
- Lots of new diagnostics added to regression suite. We now have over 200 diagnostics in this
regression.
Special note: Please note that the CDD file format for this release has changed from previous
CDD files and is therefore incompatible with older versions. If you try to read a CDD file
generated from an older version of Covered with the newer version, Covered will tell you that
this cannot be done due to incompatible CDD versions.
* 11/16/2003
Release covered-20031116 made. This development release contains a new way to specify FSMs
within the design by using inline Verilog-2001 attribute syntax. There are also a lot of
bug fixes contained in this release as well as the usual user and development documentation
enhancements. See the list below for more details on the changes made for this release.
- Added better VCD parsing capability to allow bit selects to be "attached" to the signal
names in the VCD variable definition section. The newer versions of Icarus Verilog now
output this format style.
- Added ability to specify FSM location and transition information using Verilog-2001
attributes. Added many diagnostics to regress suite to verify this capability.
- Fixed bug found in stable release that caused an incorrect calculation of unary operations
performed on single-bit values. Fixes bug 835366.
- Fixed bug found in using constant values in the right-hand side of repetitive concatenation
operators. Fixes bug 832730.
- Fixed bugs in reporting of FSM coverage information in the report command.
- Fixed bug in FSM variable binding stage that caused incorrect coverage numbers to be reported
for FSM coverage.
- Fixed bug in handling variables that are too long (more than the allowed 1024 bits). Removes
memory corruption problems when this occurs. Displays warning to user that it has found
a variable that it cannot handle and gracefully disregards any logic that uses these variables.
- Updated user documentation to include new chapter on inline attributes that Covered can
now handle.
- Updated development documentation for new functions added in this release.
* 10/19/2003
Release covered-20031019 made. Lots of modifications to existing structures and supporting
code to increase scoring speed. In my testbenches, I am seeing about a 3-4x improvement
in speed. Additionally, code enhancement for allowing bit selects and signal concatenations
in command-line FSM variable descriptions are now allowed. User documentation has been
updated for these changes. Some bug fixes are also included in this release. The
following list shows the changes from last development release.
- Added ability to parse more complex state "variables". This includes the ability
to specify single and multi-bit signals and the ability to concatenate more than
one signal (or signal bit select) to make a state variable. Please see user
documentation for more information on this.
- Minor tweaks to report format for displaying filenames (only basename of filename
is output instead of the entire path).
- Fixing bug in VCD parser to allow bit select parsing of a variable when the
variable name and bit-select information are not separated by spaces (this is something
that newer versions of Icarus Verilog now does in its VCD files).
- Changed structure for vectors from ints to chars. Each vector element stores information
for one 4-state bit value and its coverage information (instead of storing 4 4-state
variables and coverage information). This reduces memory needed and increases calculation
speed on vectors.
- Fixing bug in signal_from_string function.
- Fixing bug in arc.c related to non-zero LSBs of signals.
- Added new parameter to info line in CDD file that specifies the format of the CDD file.
This is used by Covered to keep CDD files with different formats from being merged, read,
etc.
- Removed LSB information from vector and storing this information in the signal
structure. Reduces memory required, enhances speed, and fixes existing bugs with bit
selects.
- Added more diagnostics to regression suite to test new functionality.
- Updated user documentation for new changes.
* 09/25/2003
Release covered-20030925 made. This release contains the first working FSM code
coverage portion in Covered. There is a lot more to work on in the FSM code coverage
area in the way of automatic FSM extraction and state transition specification, but
this version is able to extract FSM coverage information for an FSM that is located
by the user. Please see user's manual for this release for more details on specifying
FSM location. Summary and verbose reporting are available for FSM coverage at this
point. Additionally, the data format for FSM coverage information in the CDD file
has been finalized. FSM coverage merging is also supported in this release. User and
development documentation has been updated. Please give this development version a
go to get any bugs out of the FSM code coverage engine.
In addition to the FSM coverage support, a bug was fixed in the vector_to_int()
function when converting a vector whose LSB is a non-zero value.
Here is what is on the horizon for FSM coverage that you should expect to see in the
coming development releases.
- Ability for user to specify the location of an FSM using $attribute function.
- Ability for user to specify all possible state transitions for a given FSM on the
command-line and using inline $attribute functions.
- Automatic FSM extraction including locating an FSM and extracting all possible
state transitions.
* 08/20/2003 - Stable Release 0.2.1
Some bugs were found in the covered-0.2 release that needed to be fixed to consider
Covered to be completely stable. This release (covered-0.2.1) contains these fixes
which are outlined below. Please get a hold of this stable release if you have already
downloaded covered-0.2.
- Fixing bug with the initialization of the new symtable structure. Only 255 of the
256 children of each node were being initialized correctly. Fixes a segfault problem with
the symtable_dealloc routine.
- Fixed memory leak problem with file list in parser. This was a long outstanding problem
that has now been understood and fixed.
- Added fclose() after the VCD parsing was complete.
- Fixed a memory problem with the symtable structure that caused other data structure
values to be corrupted.
- Fixed assertion error problem with VCD symbol aliasing.
* 08/16/2003
Stable release covered-0.2 finally made! This release will be the springboard
for adding FSM coverage code, code optimizations as well as a few new features
that should make the score command run much faster. Some important bug fixes
were made in this release and code optimizations have been added to the score
command. If you are getting coverage for a larger design, you should definitely
notice the speed increase. In one of my designs, the speedup was a facter of
a bit more than 3x. The following are the list of changes made for this release.
- Added -ts option to score command to allow the user to see where in the
simulation process the score command is currently at. Please see user
documentation for more details on this new option.
- Fixed bug with multiple wait event statements within same always block.
This means that the CDD files created with the last version of Covered
will be incompatible with the new CDD files.
- Fixed bug with posedge, negedge and anyedge expressions when more than
one of these is found in the same always block.
- Fixed bug in vector comparison function. Vectors will now compare to a value
of true if the values of two vectors (whose bit size is different) are equal
up to the smallest MSB of the two vectors. Before, if two vectors were not
of equal size, a compare would always evaluate to FALSE.
- Removed unnecessary global variables.
- Removed generated development documentation from release and opted to
generate these with a user 'make' in the doc directory (makes release size
smaller and is unnecessary for most users anyways).
- Development documentation updated.
- User documentation and man file updated.
* 08/06/2003
Release covered-0.2pre3 made. It has been quite a while since a release has been made
which has been due to a particularly tricky bug that was found with non-blocking
assignments. This bug generated bad coverage information (this is considered very bad!)
This release contains bug fixes and development documentation updates. If no more problems
are found with this release, I will get the 0.2 release made very soon. The following
is a list of the changes for this release.
- Fixes to line.c and toggle.c to provide better cross-platform support.
- Lots of updates to the development documentation.
- Fixed bug with properly handling hierarchical references in expressions.
- Fixing bug with single-bit parameter handling (caused a diagnostic miscompare
between Linux and Irix OS's).
- Fixed non-blocking assignment bug. This bug affected the order of execution in
Covered's simulator which resulted in bad coverage information being generated.
- Fixed bugs in divide, mod, left shift, right shift and some other expression types
to avoid converting variables that have unknown values to integers (which results
in Covered errors at run-time).
The list of changes is short, but the changes made are very necessary to getting reliable
coverage numbers from Covered. Please get a copy of this version and test it out so that
we can get the stable 0.2 release made ASAP.
* 02/18/2003
Release covered-0.2pre2 made. Bug fixes and enhancements for allowing more Verilog
code to be parsed without spewing parsing errors. The list of open bugs is empty at
the moment. I will be working on enhancing the user documents and development
documents in preparation for the stable release. The stable release will be made
next unless there are new bugs found for which the bug fixes convince me that additional
testing is necessary. The following is a list of the changes for this release.
- Fixed bug with copying instance trees for instances of modules that were previously
parsed and built into the main instance tree.
- Fixing bug in file finder so that only missing modules are displayed after the
parsing phase is completed.
- Updated output of filenames as they are parsed to give more consistent look.
- Fixing bug with leftover tmp* file when missing module error is reported.
- Adding parsing support for pullup, pulldown and gate types though these are not
supported for coverage at the current time (probably will be supported after stable
release).
- Adding parsing support for real numbers in statement delays.
- Fixing case where statement is found to be unsupported in middle of statement tree.
The entire statement tree is removed from consideration for simulation.
- Added preliminary support for parsing attributes though the parsing support is not
complete at this time.
- Fixing bug with line ordering where case statement lines were not being output
to reports.
- Fixing bug with statement deallocation for NULL statements within statement trees.
- Updates to parser for new bison version 1.875
- Added support for named blocks
- Fixing bug with handling of preprocessor directives with leading whitespace.
- Fixes/optimizations to db_add_statement function which avoids stack overflow errors.
- Added check in regard to -i option to score command. Bad -i values would cause no
coverage information to be generated but would not tell user explicitly. Error
message now provided with -i option is not specified but is needed and/or -i option
is incorrect.
- Lots of parser updates to be able to parse UDPs, escaped identifiers, specify blocks,
and some other various Verilog code that was causing parse errors or assertion errors.
- Fixed proper handling of the event type.
- Fixed bug with merging constant/parameter vector values which caused assertion error
in report command when reporting on a merged file.
- Fixed user error message for merge command when CDD files are unable to be read.
- Added new type to CDD for general CDD file information. This allows CDD files from
different testbenches with the same DUT instantiated to be properly merged.
- Fixed problem with generating report from CDD file that has not been scored. Covered
detects that the CDD file has not been scored and outputs an error message to the user
not allowing them to generate these reports.
- Added support for reading bit selects from VCD files (this information was previously
ignored). This was necessary as other simulators bit blast module ports in VCD files.
- Updated look of instance reports to display full hierarchy of an instance instead of
the instance name and the instance name of the parent module. Much easier to locate
the instance in the design now.
- Fixed bug with using -D/-Q option with merge command.
- Added merge regression testing capability to regression suite.
- Updated build environment for RedHat 8.0 requirements.
- Updates to regression suite
- Development documentation updates.
The way that Covered looks and feels for 0.2 stable release is set in stone now. Please
make sure that you test this version as much as possible to get any leftover bugs out of
the code. I only plan on updating documentation, adding code comments, and fixing bugs.
If any bugs are sent in, a 0.2pre3 release will be created, otherwise, I will make
the 0.2 stable release available.
I've got some exciting things in Covered's future in plan after 0.2 stable release,
including FSM support, new text report look, code optimizations, support to be fully
Verilog-2001 compliant, a parallel scoring algorithm, and a new GTK+ interface.
Happy testing!
* 01/05/2003
Happy New Year! Release covered-0.2pre1_20030105 made. This release is primarily a
bug fix release; however, many of the bugs required larger changes than would be
expected before a stable release. The most significant change being to the lexer which
is now split into a preprocessor and a normal lexer (before these two functions were
combined into one). As such, this is the first prelease with a second release most
likely expected before stable release. The following is a list of changes included in
this release.
- Preprocessor split out from lexer to allow proper handling of defined values within
code.
- Added -p option to score command to allow user override of preprocessor intermediate
output file.
- Fixed bug where report output was not squelched when -Q global option specified on
report command line.
- Modified regression suite to verify CDD file generation (was being performed before),
module report generation (new) and instance report generation (new) to make sure that
report output was consistent.
- Fixed bug where integer, time, real, realtime and memory data types used in expressions
where considered to be implicitly defined and given 1-bit values. When these types
are seen in expressions now, they are ignored by Covered (caused nasty segfault).
- Fixed bug when a parameterized module is instantiated more than once in a design
(sent error message to user when this occurred).
- Fixed bug where a parsed module that was required but not at the head of the module
list was not being found by the parser.
- Added internal assertions and code to verify that we never try to overrun arrays
in the VCD parsing/running stage (caused nasty segmentation fault).
- Reorganized code for symtable symbol lookup and value assignment.
- Fixing bug where a parameterized module that was instantiated in a design more than
once was not getting the correct parameter value(s).
- Fixed module search algorithm to reparse a Verilog file that contains a module
that was previously ignored (not needed at the time) but is later found to be
needed.
- Created tree.c and tree.h to handle new module search algorithm and to replace
preprocessor define tree structure.
- Updated development documentation.
- Updates to user manual and manpage for new -p option, notes from this release
and a new section that starts to describe what logic is analyzed by Covered and
which code is not analyzed.
I've got some fairly large designs being run with this version of Covered and the regression
suite has grown to over 130 diagnostics with more on the way. Keep the bug reports coming!
Release notes for the gEDA/gaf 20040111 snapshot
Changes
_________________________________________________________________________________________________________
General / Summary
* Lots of changes in most areas. This release contains the largest amount of changes in quite a while.
Expect bugs, crashes, and general instability. If you tell me about them, I might be able to fix them.
* Probably the biggest set of changes were the addition of multi-line text support. The bulk of the work was
done by Carlos. The text add dialog box and the multi attribute add/change dialog box both support the
adding and editing of multi line text items, however, I am going to change these dialog boxes in a
subsequent release to be a little like the old behavior, but still support multi-line text support. Full
multi-line text support requires that you use gtk+ 2.2.x.
* Also part of the above changes was to get rid of some fixed sized buffers within libgeda and gschem.
Hopefully I have hashed out all the bugs in these changes, but I wouldn't be surprised if I missed
something. Please report all crashes. Thanks.
* Changed the file format a little. Changed the way sch/sym files are versioned and added a field to the
text item to support the multi-line text feature addition. I recommend everybody run gsymupdate and
gschupdate (and verify the resulting files!) to get rid of the log warning message. gEDA/gaf will always
write the new file format for all saved schematic/symbols.
* The v flag (the version of the sym/sch file), in the past, was keyed off of a version date, such as
20030901. Starting with 20040111, I am no longer using this date as the version of the sch/sym file, but
rather I added a new field (number) which is the file format version. The new version line looks like:
v 20040111 1
This is nice that I don't have to update all the symbols, schematics, etc... to get rid of a log warning
message. The current version of the file format is 1. All past files are versioned as 0. As an experiment,
I left all the symbol files at v 20031231 1 and nobody should care/notice. I am planning more changes to
the file format in subsequent releases and this version field will make changing it easier.
* The text object has an additional field which is the number of lines (N) the text item contains. The text
item is then followed by N number of lines of text. Example:
T 48400 59900 9 10 1 0 0 0 3
Line1
Line2
Line3
* The component libraries:
vhdl, verilog, new asic, and the new gnetman
are commented OUT in the system-commonrc file. I did this because there are significant symbol name
clashes between these libraries. If you want to use one of these libraries, please place the appropriate
(component-library "...") string in some rc file. This commenting out is temporary, till I fix the
component name clashing bug (jitterbug#9).
* The component-library-search keyword in the system-commonrc file was commented out. If a directory is
specified for the component-library-search keyword, then libgeda/gschem/gnetlist will automatically find
any directories in the specified directory and add them to the component search path. By having this
keyword in place, this would have undone the above commenting out.
If gschem/gnetlist cannot find your custom component libraries after upgrading to 20040111, then either
comment in the component-library-search keyword back into the system-commonrc file or explicitly add the
custom component libraries to an rc file. The latter action is prefered.
This info was added on 02/08/2004.
* Upgraded all packages to use gettext (GNU gettext) 0.12.1. I don't think that anybody who downloads the
source tarballs will need this particular version, but you will certainly need it if you build the CVS
version.
* Partially applied Carlos' UTF-8 patch for gtk+ 2.2.x. I couldn't test the complete patch, so I will keep
working on this. Moving libgeda to use UTF-8 internally is going to be a bit of work, but the sooner it
happens, the better.
* The gEDA Suite setup program has been improved considerably. It now supports the download of the tarballs
automatically using wget. All you need to get from the gEDA website is the toplevel Makefile and type:
make xinstall and the setup program will do the rest. See below in the build section for more information
on using xinstall. Please report any problems with gEDA Suite setup so it can be further improved.
* Much more documentation that gets installed now (almost all of it). I included Bill Wilson's gsch2pcb
tutorial and Russ Dill's tragesym tutorial. I also am installing all READMEs, so please see the
gedadocs.html file for almost all available documentation on gEDA/gaf. You can access this file via
Help/Manual... in gschem (make sure you have a web browser installed).
libgeda
* Shared library version number now at 20.
* In 20030901, libgeda was accidentally being built without optimization. Fixed in this version.
* Applied Carlos Nieves Onega's multi-line text patch. See below in the gschem for more info. This patch
changed and fixed a lot of things in libgeda, so expect some instability.
* Applied a few more patches by Carlos to perfect the multi-line text support in libgeda (mainly dealing
with support for tabs in multi-line text items).
* Added postscript output for mutli-line text items. This support is really new and not 100% perfect. Expect
some problems here, mainly when you start rotating and changing the alignment of many line text items.
Putting tabs into the text strings is not yet supported.
* Fixed a really nasty bug in o_attrib_get_name_value() which was caused by g_strsplit() not behaving the
same between glib 1.2.x and glib 2.2.x. Be careful when using g_strsplit, especially if you use both
versions of glib. Bug caught by Stuart.
gschem
* Added the --with-stroke command line to specify where ./configure can find the libstroke files.
* Changed the behavior of the print dialog box to close when the user presses the Print button.
* Added the ability to generate PNGs from the command line. Look at gschem/scripts/image.scm for the scheme
script. Command line looks like: gschem -o test.png -s image.scm filename.sch
* Added a schem rc keyword: image-size which lets you set the size of the PNG image generated using the
above guile script.
* Applied Carlos Nieves Onega's multi-line text patch. This patch adds multi-line text support to
gschem/libgeda. This patch made some very deep changes to internals which haven't changed in years, so
expect some instability. Multi-line text is properly supported only when using gtk+ 2.2.x. You will be
able to load schematics and edit multi-line text (in a limited fashion) if you use gtk+ 1.2.x
* Part of the above patch was the removal of a bunch of fixed sized buffers. Hopefully Carlos and I have
fixed all issues surrounding these changes, but expect some instability here as well as we work out the
kinks.
* Applied a patch by Carlos to highlight the proper alignment value in the pull down menu in the Edit
Text... dialog box.
* Fixed the visual alignment of the menu items and hotkeys when using gtk+ 2.2.x.
* Improved the appearance of a few of the dialog box, by mainly adding whitespace. A few dialog box got a
few more touch ups, but nothing too drastic.
* Applied a patch by Carlos to add multi-line attribute editing to the multi attribute dialog box. The
changes for this are not complete and will change in the next release.
* Updated the pt_BR.po with Antonio's UTF-8 version.
* Applied Stuart's multi-select open patch. Now you can select multiple schematics to open using the
File/Open... dialog box. Hold down the shift or control key as you click on filenames.
* Part of Carlos' multi-line text patch was to change the quick rendering of text from a line to a
rectangle. Refined and refactored this code a little to properly display attributes.
* Fixed a long standing bug in the File/Open... and File/Close... mechanisms when dealing with multiple
windows. Bug identified by Karel Kulhav.
* Fixed a long standing bug in the preview window (for schematics and components) where there would be
garbage data in the bottom of the window. The bug only manifested itself under very specific conditions
and only when using gtk+ 1.2.x. I'm quite surprised nobody else complained about it (or rather recently).
* Applied a patch by Carlos to support the new Spanish characters.
* Fixed the invalid scrollbars on startup bug.
* Updated the man page a little bit. Added code to the build mechanism to generate an html version of the
man page, which is installed into the documentation directory.
* Bunch of other improvements and bug fixes.
gnetlist
* Upgraded Bill Wilson's gsch2pcb gnetlist backend to the latest (1.4)
* Applied all of Carlos' DRC2 patches.
* Applied all of Stuart's spice-sdb patches. The included spice-sdb backend should be Stuart's absolute
latest version. A bunch of improvements to various parts of gnetlist were included in these patches.
* Applied of Stuart's patch to the partlist backends.
* Updated the man page a little bit. Added code to the build mechanism to generate an html version of the
man page, which is installed into the documentation directory.
* Added the scheme rc keyword: unnamed-netname which lets you control what the unnamed nets should be
called.
* Add the necessary rules to the Makefiles to install all the backend READMEs into the documentation
directory.
* Applied a patch by Christopher K Eveland to fix a condition where gschem2pcb was picking up a pin when it
should not. If somebody could test gschem2pcb on an existing project and make sure it still works as
expect, it would be greatly appreciated.
* Added the Racal Redac format backend by W. Kazubski.
* Added the new RF Cascade and futurenet2 backends by Dan McMahill.
* Applied a bunch of patches by Dan for doing net aliasing/renaming. These patches touched the C files as
well as various backends.
* Applied a few more patches by Dan to fix some m4 quoting issues with the PCB backends.
* Bunch of other minor bug fixes.
gsymcheck
* No significant changes (lots of pending work though).
* Updated the man page a little bit. Added code to the build mechanism to generate an html version of the
man page, which is installed into the documentation directory.
symbols
* Werner Hoch has fixed a whole slew of symbols in various component libraries. Thanks Werner!
* Added a whole bunch of contributed symbols from various people. Thanks.
* Added a bunch of new Spanish characters by Carlos.
* Removed vhdl, verilog, asic, and gnetman from the system-commonrc file.
geda (gManager)
* Piotr Miarecki added a bunch of features and fixed a few bugs in gManager. Give it a try and let him how
gManager works for you. gManager is looking really nice.
* Integrated Antonio's pt_BR translation. This should work now.
* Added a strategic sleep to the mainloop of gManager to reduce the CPU load.
utils
* Updated Bill Wilson's gsch2pcb to version 1.4
* Add the necessary rules to the Makefiles to install all the backend READMEs into the documentation
directory.
* Integrated Stuart's garchive script.
docs
* Applied a whole bunch of patches from Dan McMahill to the symbol creation guide. These patches added/fixed
information related to the footprint= attribute.
* Started using hyperref.sty for all LaTeX generated documentation, which adds hyperlinks to the pdf files.
* Added a bunch of converted txt -> tex documents. The conversions were done by Dan McMahill.
* Added the Dan McMahill's documentation for the RF Cascade gnetlist backend.
* Rewrote the toplevel gedadocs.html index file to link all the new documentation, readmes, man pages, and
tutorials. The gedadocs.html now file contains almost all existing documentation on gEDA/gaf that I'm
aware of.
* Added a couple of tutorials that people have written. Namely Bill Wilson's gsch2pcb and Russ Dill's
tragesym tutorials. Both of these tutorials are accessible from the gedadocs.html file.
* Explicitly stated in the file formats document that all the file formats associated with gEDA/gaf are
covered by the GPL version 2.0.
* Lots of improvements and fixes to various docs.
examples
* No significant changes.
For more a detailed changes, please look in the appropriate ChangeLogs in the source tarballs.
Changes:
Library Management
* Packages and Device Sets can now be copied into the currently
edited library from other libraries, either through Drag&Drop from
the Control Panel or by using the COPY command's new extended syntax
(see "Help Copy").
* New package variants can now be created by directly using packages
from other libraries, either through Drag&Drop from the Control Panel
or by using the PACKAGE command's new extended syntax.
* The packages of the currently edited library can now be updated with
those from other libraries, either through Drag&Drop from the Control
Panel or by using the UPDATE command's new extended syntax.
And more! please review this link to see a full list of changes:
http://www.cadsoft.de/version41.htm
A partial list of what's new is:
- Internal resolution changed to 0.01 mil from 1.0 mil
- Improved DRC checking
- Mirroring/rotating of buffers
- Undo works on trace optimizations
- Fixed polygon undo bugs
- Fix arc DRC bugs
- Added local measurement for line drawing
- Added mode for polygon viewing to help examing planes
- Added new footprint libraries (amp, amphenol, bourns, johnstech,
minicircuits, panasonic)
- Added new footprints to the geda library
- Other bug fixes
Gnucap 0.34 release notes (02/01/2004)
This is a bug fix and compatibility release.
1. Fix bug causing incorrect interpolation of backwards tables.
2. Fix tanh overflow bug.
3. Fix some parsing bugs.
4. Fix occasional "double load" bug.
5. Fix AC sweep with one point.
6. Transient start time really works.
7. Fix occasional assert fail after option short is changed.
8. Fix memory leak resulting from failure to delete unused common.
9. Fix a Z probe bug that sometimes gave wrong answers.
10. Fix a limiting bug that sometimes caused non-convergence.
11. Configure handles isnan.
12. Improvements to logic initialization. It is still not correct.
Some things that are still partially implemented:
1. BSIM models, charge effects, "alpha0" parameter. (computed then
ignored)
2. Configure still doesn't handle everything.
3. The model compiler still requires too much raw coding.
4. Named nodes. If you set the option "namednodes", it will support
named nodes, but some things don't work, so it is off by default.
5. The preliminary IBIS code is now included. For now, it is a
standalone executable, that reads an IBIS file and generates a
netlist. The netlist requires some editing to use, and is not fully
compatible anyway. It is included in hopes of recruiting help in
finishing the project.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. An occasional bogus calculation in MOSFETS occurs when a device is
reversed. This sometimes causes nonconvergence.
3. Initialization is strange when repeating an analysis without an
intermediate edit.
Hot items for a future release (no promises, but highly probable):
1. Verilog-AMS and VHDL-AMS support.
From the NEWS file:
This release is basically a 0.2.1 release with the available bug fixes
patches applied to it. This should make getting a stable release less
tedious.
rather than using LOWER_OPSYS. This is because the couple of os's
that had correct targets were the same and others that pkgsrc works on
aren't listed at all (like solaris). Fixes build problems noted on
solaris.
-- Release 0.15 --
2003-10-06 Stefan Petersen <spe@stacken.kth.se>
* src/draw_amacro.c: Drawing of aperture macro primitive 7 was
severly broken. Revealed by Drew Moore who sent an example
along. Thanks Drew! Closes bug #818307.
2003-09-28 Stefan Petersen <spe@stacken.kth.se>
* src/gerber.c: Patch from Peter Brueckner. Some Gerbers don't
have G04 but just G4. Peters patch fixes that for G- and M-codes.
2003-09-08 Stefan Petersen <spe@stacken.kth.se>
* src/gerber.c: Patch from Simon Munton to fix a problem with polygons
sometimes not being filled properly. Closes bug #800928 (which
he promptly had submitted).
* src/gerber.c: Another patch from Simon. This time it fixes
circular polygon outlines by with a number of short segments.
Closes bug #603183, which was almost a year old. Thanks Simon!
curses.buildlink2.mk. This was wrong because we _really_ do want to
express that we want _n_curses when we include the buildlink2.mk file.
We should have a better way to say that the NetBSD curses doesn't
quite work well enough. In fact, it's far better to depend on ncurses
by default, and exceptionally note when it's okay to use NetBSD curses
for specific packages. We will look into this again in the future.
Inspired by FreeBSD "ports".
Fix the PLISTs accordingly.
Also, while at it, remove now obsolete compileall.py calls in post-install
targets and insure that extension.mk is in included before builinlinks of
other Python modules.
Discussed with/ok'ed by drochner@.
This update is a collection of little improvements and a significant
verhaul of hardcopy plot and export.
Hardcopy and documentation output can now be obtained using either graph
or Gnuplot. A dialog box allows choosing output formas and a few other
settings. Additional plot/export filters can be plugged in by writing a
suitable scheme module.
There's a data-export function for extracting and saving a subset of a
datafile as ascii.
The stacking/drawing order of waveforms can be changed.
Selected waveforms are now drawn in a highlighted style.
USE_GCC2 or USE_GCC3 where appropriate.
the functionality of the old gcc.buildlink2.mk has been rolled into
compiler.mk now, which is automatically used.
more changes to come later...
Release notes for the gEDA/gaf 20030901 development snapshot
------------------------------------------------------------
CHANGES:
General / Summary
* The biggest change in this release is the addition of gtk+ 2.2.x
support. Now you can build gEDA/gaf with either gtk+ 1.2.x or
gtk+ 2.2.x. Some programs like setup and geda still require
gtk+ 1.2.x, but that will be fixed in a future release.
The original gtk+ 2.2.x patch was by Ye Ma (Thanks!).
* Added --with-gtk12 commandline flag to all ./configure scripts
to force the use of gtk+ 1.2.x. Just add this to the opt=
variable in the toplevel Makefile to force all of gEDA/gaf to
use gtk+ 1.2.x instead of gtk+ 2.2.x. The default used gtk+
library if both 1.2.x and 2.2.x are installed is gtk+ 2.2.x.
* In order support above, pkg-config is now REQUIRED to successfully
./configure the packages. pkg-config is also required if you
are building/linking against gtk+ 1.2.x. You can get pkg-config
from either:
[1]http://www.geda.seul.org/dist
or [2]http://www.freedesktop.org/software/pkgconfig/
* If you do not keep all of your packages installed in one
place or if it is not in a standard location (like
/usr/lib/pkgconfig), then you must tell pkg-config where
to look by using the PKG_CONFIG_PATH environment variable.
I keep all of my *.pc files in /usr/local/lib/pkgconfig,
so my PKG_CONFIG_PATH is set like this:
export PKG_CONFIG_PATH=/usr/local/lib/pkgconfig
* Rewrote and simplified all the ./configure.ac files. Here are
the versions of the auto* tools I use:
autoconf (GNU Autoconf) 2.54
automake (GNU automake) 1.7.1
ltmain.sh (GNU libtool) 1.4.2
aclocal (GNU automake) 1.7.1
gettext (GNU gettext) 0.11.5
If you use any other versions, good luck. :-)
libgeda
* Shared library version number now at 19.
* Removed libgeda-config, replaced with libgeda.pc (pkg-config file).
In order for gschem and the other libgeda programs to find this
file during the ./configure stage, you must set the PKG_CONFIG_PATH
environment variable to something like this:
export PKG_CONFIG_PATH=$HOME/geda/lib/pkgconfig:$PKG_CONFIG_PATH
The settings for this variable is printed when you type 'make'
in the upper most directory (toplevel) where you untarred all
the source tarballs.
* libgdgeda 2.0.15 is now required to build libgeda.
* No significant code changes.
gschem
* Applied Carlos Nieves Onega's multi attribute patch. With this
patch, the multi attribute add/edit dialog box behaves a lot
more intelligently when adding or changing attributes.
* Bunch of work to support both gtk+ 1.2.x and 2.2.x.
* Rewrote the exit dialog box to look better under both 1.2.x
and 2.2.x. Quite a few of the dialog box look bad under
1.2.x, but look absolutely dreadful under 2.2.x, so they
will be recreated (and hopefully improved in the process)
in future releases.
gnetlist
* Applied Carlos Nieves Onega's commandline (-l filename) load
scheme patch. The scheme code is loaded and executed from the
specified file before the backend is loaded.
* Added the -m commandline flag which allows scheme code to be
loaded from a file after the backend is loaded but before it is
executed.
* Integrated Carlos Nieves Onega's DRC2 backend.
* Applied Carlos Nieves Onega's warning cleanup patch.
* The required work to get gnetlist to work with both gtk+ 1.2.x and
2.2.x.
* Added Bill Wilson's gnet-gsch2pcb backend.
* Applied Stuart Brorson's latest changes to the spice-sdb
netlister. His changes included the -s command line flag
(sort output netlist) and the gnetlist:get-calling-flags as
well as improvements to the spice-sdb backend itself.
gsymcheck
* No significant changes other than the gtk+ 2.2.x support changes.
symbols
* Werner Hoch updated a bunch of symbols in various directories
including memory and 74.
* Removed gesym-config. The new ./configure.ac files do not use
this file anymore.
* Added a bunch of contributed symbols (not all though, some are
still pending for various reasons).
* The author= and email= attribute on five symbols have been
merged into one (author=).
geda (gManager)
* No changes
setup
* No changes
utils
* Finally integrated Werner Hoch's tragesym 0.0.5 into the
utils package. tragesym is a symbol creator for gEDA/gaf written
in python.
* Applied patch by Holger Dietze to update gmk_sym to be current.
* Integrated Bill Wilson's gsch2pcb package.
gsch2pcb is conceptually based on the gschem2pcb shell script
distributed with gnetlist, but additionally handles multiple
schematics, handles element file footprints, and removes pc
board elements corresponding to components deleted from the
schematics. It also forward annotates component value changes
* The necessary changes to support gtk+ 2.2.x.
* Integrated pads backannotation script by Dan McMahill.
A perl program which implements backannotation from Pads
PowerPCB board layouts to gschem schematics.
docs
* Documented the merge of author= and email= (suggestion by
Werner Hoch)
* Updated spice-sdb document with a the latest version from
Stuart Brorson.
* Added Dan McMahill's documentation for the pads_backannotate
script.
examples
* No changes.
For more a detailed ChangeLog please look in the appropriate source
directories.
From the CHANGES file:
254 v3.1 rev 19 8/12/03
Required reconfiguring without Tcl once to generate the
"Makefile.in" in the Xw directory; otherwise, automake 1.7
becomes a requirement.
253 v3.1 rev 18 8/6/03
A fix to the output, correcting the page numbering in the
PostScript page headers. The incorrect numbering can cause
some printers to lock up. . .
252 v3.1 rev 17 7/14/03
Thanks to Ted Roth for fixing my rather too-hasty fix of
revision 16. Also: Some fixes to the autoconf script (also
from Ted Roth), and autoconf script updated to work with the
latest versions of autoconf/automake/aclocal.
for a possessive (like her, his, whose, their, and its).
Note that I didn't check for proper use of "its" (when it should
be "it is" or "it has" instead).
I also saw over 15 other grammar or punctuation problems, but not
fixed in this commit.
Covered is a Verilog code coverage analysis tool that can be useful
for determining how well a diagnostic test suite is covering the
design under test. Typically in the design verification work flow, a
design verification engineer will develop a self-checking test suite
to verify design elements/functions specified by a design's
specification document. When the test suite contains all of the tests
required by the design specification, the test writer may be asking
him/herself, "How much logic in the design is actually being
exercised?", "Does my test suite cover all of the logic under test?",
and "Am I done writing tests for the logic?". When the design
verification gets to this point, it is often useful to get some
metrics for determining logic coverage. This is where a code coverage
utility, such as Covered, is very useful.
Please note that this package is for a stable release version.
There is a seperate package (covered-current) which is made of
development snapshots.
Changes since 0.13:
* Removal of the last inclusions of malloc.h after tips
from Charles Lepple.
* Some patch that fixed a problem for Larry Doolittle
* Error messages when running RS274D instead of
"crash-and-burn" (ie segfault).
Pcb - X11 interactive printed circuit board layout system.
Pcb is a handy tool for the X Window System to design printed
circuit boards. All coordinate units are 1/1000 inch.
Please note that this package is a development snapshot and while it contains
the latest and greatest features, it may be buggy as well. There is a seperate
pcb package which is made of the stable releases.
(disable it), and another one to use memory a bit more efficiently.
The program is now usable with VCD files larger than 10M.
Update to the latest snapshot to ease discussion with the author;
a notable change in this is improved LXT support.
* Changes in Dinotrace 9.1k 06/06/2003
**** Fix crash with busses that are replicated with different widths.
* Changes in Dinotrace 9.1j 03/22/2003
**** When window is resized, keep same percentage of trace visible.
**** Fix File Reread duplicating signals. [Uwe Bonnes]
**** Fix File Reread with identically named signals.
**** Fix dropping of 0s on signals > 32 bits. [Jason Mancini]
**** Fix coredump on read and GCC 3.2. [Jason Mancini]
Release notes for the gEDA/gaf 20030525 development snapshot
------------------------------------------------------------
CHANGES:
General / Summary
* This release is mainly a packaging release. Several
contributed pieces were integrated into the gEDA/gaf
release framework including:
- Piotr Miarecki's geda (gManager)
- Piotr's gEDA Suite setup.
- geda-examples which is a tarball of various
examples of gEDA/gaf in action.
* Two new backends were also incorporated (switcap and spice-sdb)
* Improved the toplevel Makefile a little bit. Now if you are
building from a CVS checkout, you can: 1) set the PATH and
LD_LIBRARY_PATH variables (as usual) and 2) type: make install
and the Makefile will take care of running auto* as required.
libgeda
* Shared library version number still at 18 (unchanged).
* No changes for libgeda.
gschem
* Applied patch by Mario Klebsch for bug #43: "If gschemdoc is
not install, gschem crashes".
* Fixed a crash when you press the q key or any other "no-action"
key. This was changed behavior when using guile 1.6.3.
* Added "reset-component-library" and "reset-source-library" rc
keywords. Now from either ~/.gEDA/gschemrc (or gnetlistrc)
or a local gschemrc (or gnetlistrc) file, you can empty out
all the default libraries and set your own.
* Fixed the x_multimulti.nw build problem that some people ran into.
* Updated the Brazilian translation (new file supplied by Antonio).
gnetlist
* Applied a patch by Dan McMahill to get the PCBboard backend working
with guile 1.6.3
* Integrated Stuart Brorson's advanced spice backend (spice-sdb).
Please see the howto in the docs directory (docs/spice-sdb/)
for more info on this backend. The only changes I made to
Stuart's original code was to lowercase the name of the backend
(from spice-SDB to spice-sdb). Also check out his spice website
at: [1]http.
* Integrated Dan McMahill's switchcap backend. Please see the
gnetlist/docs/README.switcap for more info. Also see the
documentation in the docs package (docs/switcap) for even more
info.
* Applied a patch from Dan to the gnetlist.1 manpage.
gsymcheck
* No changes for gsymcheck.
symbols
* Werner Hoch updated a bunch of symbols in the max symbol library
along with adding a few new symbols. Thanks!
* Integrated a few new symbols for Stuart's spice backend.
* Integrated a few new symbols for Dan's switcap backend.
* Fixed 93Cx6-1.sym to include power information (patch by
Holger Dietze). (Bug#65)
* Applied Wojciech Kazubski's --with-docdir patch. Now you can
specify where the documentation is installed using --with-docdir
at the ./configure stage.
* Fixed 74/7408-2.sym and 74/7409-2.sym, these symbols were swapped.
Pointed out by Mario Klebsch.
* Integrated a bunch of symbols from various people (thanks)
who used the website upload mechanism. Btw, the website symbol
upload is so much easier for me, so please continue using it.
I think I have a few symbols I still need to finish integrating.
geda (gManager)
* From the README:
"gEDA Suite Project Manager is a start point for
everything what you may want to do. It is used to
organize your files and easy running tools. It
simplifies your job."
Even though it is called gManager or Project Manager, the
built executable is called "geda". Please play with it and
let Piotr know of any suggestions or bugs.
* This is the first release of this program inside the gEDA/gaf
framework.
* Integrated this program into the toplevel Makefile (so that it gets
built when you type make install etc...)
* If you build using the toplevel Makefile from now on, you must
have geda in the current directory.
setup
* This is Piotr's gEDA Suite Setup program.
* This is the first release of this program inside of the gEDA/gaf
framework. Please send all bug reports to Piotr.
* Here's how you use it:
1) Download all the gaf files and the required libraries
and put them all into one directory.
2) Download guile-1.4.1.tar.gz and put it also into the
above directory.
3) Type: make xinstall
4) Follow the GUI.
Setup will build and install all of gEDA/gaf. Eventually this
will be extended to build/install the rest of gEDA and gEDA
related programs. Please let Piotr know of any suggestions or
bugs.
Make sure you have guile-1.4.1.tar.gz in the current directory
along with all the gaf tarballs.
* If you build using the toplevel Makefile from now on, you must
have setup in the current directory.
utils
* Applied a patch by Charles Lepple to fix a build problem on OSX.
* Applied Wojciech Kazubski's --with-docdir patch here as well.
docs
* Integrated documentation for Dan's and Stuart's new backends.
* Applied Wojciech Kazubski's --with-docdir patch here as well.
examples
* This is the first release of the example package inside of
the gEDA/gaf framework.
* This package includes:
- Stefan's gTAG : An example of hierarchical schematics using gaf.
- Terry Porter's lightning_detector: An example of how to use
gEDA/gaf with PCB.
- Stuart Brorson's TwoStageAmp and RF_Amp : Examples of how
to use spice-sdb for single page and hierarchical SPICE
simulation using gEDA/gaf.
If anybody else has some projects they would be willing to allow
me to distribute, please let me know! I'm always looking for
examples of gEDA/gaf in real use.
* The examples are not installed, but the toplevel Makefile expects
the tarball to be untarred in the current directory.
For more a detailed ChangeLog please look in the appropriate source
directories.
There was a couple of snapshots since february; besides bugfixes the
major highligths might be:
-handling of real values at various places
-support for library modules (esp cadence PLI1)
-better FPGA support (esp Virtex II)
-"vvp" interactive mode added
Also converted to buildlink2, and dependencies to libz, libbz2 and
readline added.
The source for version 3.1 contains the first official release of the
Tcl/Tk-based version of xcircuit. At this time , everything in the
original program has been implemented in the Tk GUI. The Tcl version
has the greatest amount of command-line control, and can be run
exclusively from the command line (e.g., from a script). A
command-line argument "-exec" has been added to facilitate running
xcircuit in "batch mode".
Starting with version 3.1 revision 10, XCircuit has been made an
official part of the EDA environment including Magic, IRSIM, Netgen,
and Tclspice. Revision 10 addresses interoperability among these
applications, including use of XCircuit in conjunction with Magic for
Layout-vs.-Schematic (LVS) verification. A Magic tutorial on using
XCircuit, Magic, and Netgen together for LVS is in the works. Note
that this EDA environment requires that all applications be compiled
with Tcl/Tk.
From this point, the embedded Python interpreter interface will not be
further developed, except for essential bug fixes and such.
now and not NetBSD-*-arm32. Changes include one or more of:
- Change MACHINE_ARCH == arm32 to also match arm
- Where ONLY_FOR_PLATFORM includes NetBSD-*-arm32, add NetBSD-*-arm
- Where BROKEN or worked around for arm gcc bugs, set USE_GCC3
The last may shake out a few more broken packages the next bulk build.
Changes since last packaged version:
Version 6.4
Graphical interface
1. Filedialog now has filters for Linux also.
Boolean algorithm (also effects booleanonly)
1. Error corrected in correction settings.
Version 6.3
Graphical interface
1. Based on wxWindows 2.3.4
2. cmake now used to create projects and makefiles
Boolean algorithm (also effects booleanonly)
1. Using the kbool library with the Boolean engine.
Version 6.21
Graphical interface
1. and it did not even save gdsii or key files properly,
i just wonder why no one did let me know ;-)
Gnucap 0.33 release notes (01/12/2003)
This is a bug fix and compatibility release.
0.32 was not widely distributed due to password problems and a heavy
work load, so the release notes are repeated after the current ones.
New features:
1. Add inductance probes, like capacitor.
Bug fixes:
1. Fix xprobe duplicate default arg bug - shows in g++3.2.
2. Fix bug that sometimes caused a crash when changing a model after
analysis.
3. Fix bug that caused an assert to fail (debug build) after removing
a probe from an element.
4. Fix a dumb typo hack bug ddHAS_READLINE. Now history and command
line editing really works. It was working, but somehow the hack
slipped into the release code.
=================================================================
Gnucap 0.32 release notes (09/30/2002)
New features:
1. Series resistance in the diode. It took 5 minutes to do,
so it is embarrasing that it wasn't done before.
2. History and command line editing, using Gnu Readline. Thanks to
Simon Hoffe for sending me the patch.
3. More parameters in the BJT model. This gives it better
compatibility with commercial simulators. These parameters are beyond
Spice 3f5.
4. "M" parameter in diode, BJT and MOS devices. M is the number of
parallel devices. Some commercial simulators have this.
Changes that may or may not be improvements.
1. The definition of the transient option "UIC" has changed. It is
now Spice compatible, which means to not attempt to do any solution or
consistency check. Just apply the values, assuming anything that
isn't specified is 0. The old behavior was to attempt a solution
while holding the IC values.
Bug fixes:
1. voltage sync bug. It still doesn't fix the MOS 2 convergence
problem.
2. Fix memory leak in POLY components.
3. Fix bug in Fourier that sometimes causes overrun (crash) and time
sync errors.
4. Modelgen: fix bug in list parsing.
5. Some changes to eliminate warnings when compiling with g++ 3.1.
6. Use Euler differentiation on first step, because trap used a value
that cannot be known then. Usually, this doesn't make much
difference, but there are a few cases where the error can get
magnified and trigger trapezoidal ringing, leading to a totally bogus
result. It most cases, you could hide it with small enough steps.
These cases should work with default settings now.
7. Fix bug that sometimes caused incorrect handling of initial
conditions (UIC),
8. Fix bug that caused continuing a transient analysis to give
incorrect results.
Significant internal changes:
1. The inductor uses all of the same support functions as the
capacitor, including "integrate", which is now correctly called
"differentiate".
2. Most of the code is in place for named nodes. It mostly works and
can be turned on with the option "namednodes". It is off by default
because it is not complete. Most likely, it will be finished in the
next release.
Some things that are still partially implemented:
1. BSIM models, charge effects, "alpha0" parameter. (computed then
ignored)
2. Configure still doesn't handle everything.
3. The model compiler still requires too much raw coding.
4. Named nodes. If you set the option "namednodes", it will support
named nodes, but some things don't work, so it is off by default.
5. The preliminary IBIS code is now included. For now, it is a
standalone executable, that reads an IBIS file and generates a
netlist. The netlist requires some editing to use, and is not fully
compatible anyway. It is included in hopes of recruiting help in
finishing the project.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. An occasional bogus calculation in MOSFETS occurs when a device is
reversed. This sometimes causes nonconvergence.
3. The "modify" command with multiple arguments seems to take only the
first one. It used to work, but is broken in this release. I am not
sure when it broke.
From the NEWS file:
* Changes in Dinotrace 9.1i 03/07/2003
*** Display values with appropriate leading 0s. [Dan McMahill]
*** Fix 0 extension of verilog values. [Dominik Strasser, Bill Welch]
Transcalc is an analysis and synthesis tool for calculating the
electrical and physical properties of different kinds of RF and
microwave transmission lines.
Transcalc was somewhat inspired by the functionality of Agilent
Technologies' commercial program linecalc. Transcalc aspires to be
more functional in the long run and well-documented with appropriate
references to formulas that are used. Transcalc is built using the
GIMP toolkit (GTK) for its GUI interface.
For each type of transmission line, using dialog boxes, you can enter
values for the various parameters, and either calculate its electrical
properties (analyze), or use the given electrical requirements to
sythesize physical parameters of the required transmission line.
Available transmission lines (this list will expand with subsequent
releases):
* microstrip
* rectangular waveguide
* coax
* coupled microstrip
* You cannot compile with backend anymore, switch is removed. In last
release this caused compilation error due to bit rot.
* Drawing of arcs is a constant headache. Mark Whitis found another
case that I had missed out. Clockwise arcs all of a sudden started
to be drawn as counter-clockwise.
* Arcs with very small angle differences could either be a complete
circle or a very small part of an arc. Calculating the angles with
integers wasn't sufficient, anyhow. They are now doubles all the way.
* Aperture macro primitive 1 was a _filled_ circle.
* Image rotate used to cause warnings that it wasn't implemented. Now
if the file has an image rotate on zero degrees there is no warning
(yes I've seen it).
* Dan McMahill discovered that if you tried to swap with an unused layer
gerbv segfaulted.
* Peter Monta submitted patch for incremental coordinates.
* No traces of Guile left...
Makefiles simply need to use this value often, for better or for
worse.
(2) Create a new variable FIX_RPATH that lists variables that should
be cleansed of -R or -rpath values if ${_USE_RPATH} is "no". By
default, FIX_RPATH contains LIBS, X11_LDFLAGS, and LDFLAGS, and
additional variables may be appended from package Makefiles.
Quick summary of changes:
- works with guile-1.6.3 now
- Norwegian/Danish/German character fixes
- PNG output now has some of the objects appearing to have the right thickness.
- added Russian translation
- bug fix in postscript output
- non-applicable menu choices are now greyed out
- fixed PADS netlist output bug
- added several components to library
- added multisheet refdes renumber utility
- several other bug fixes.
The previous version was extremely out of date and the distfile is no
longer available.
Many, many changes since the last packaged version. New 'tuner' feature
added. New models added. Several bug fixes too numerous to list.
in recent bulk builds.
Release covered-20021214 made. This release is a bug fix release. See list below
for details. Bugs that lead to infinite looping in the score command and segmentation
faults should now be cleared up. Please let me know if there are any other bugs that
need to be addressed before first stable release. Development documentation updated
to match changes in files. Regression suite has been updated quite a bit from last
time. There are now over 125 diagnostics in the regression suite (my goal was to
write about 100 before first stable release).
- Segmentation fault fixes in report command
- Parser can now handle all net types (not just wire). Diagnostics added to regression
suite to verify their proper handling.
- Parser updated to handle net declaration assignments (e.g., wire a = b & c;).
Diagnostics added to verify proper handling.
- Added human-understandable error messages in parser to help identify file and
line number along with a quasi-helpful error message description.
- When parser error is found, Covered exits after parsing phase without continuing
to write CDD file.
- Fixed bug where a multi-bit select expression existed in a module that was
instantiated more than once. Assertion error fired in this case.
- Updated regression suite for VCS testing.
- Fixed bug where parameters were used in modules that were instantiated more than
once.
- Fixed bug that dealt with parameters (see param6.1.v for test case).
- Fixed bug where a delay statement was the last statement in a statement block used
by Covered. Added diagnostics to verify correct behavior.
- Fixed infinite loop problem with db_add_statement function.
- Fixed infinite loop problem with statement_set_stop function.
- Fixed bug with parsing order. When an instance is found for a module that has
already been parsed, the instance was incorrectly being handled. Bug replicated
with instance6.v diagnostic.
- Fixed output of edge-triggered events to add @(...) around the expression (they
were easily confused with other code that could exist on the same line).
- Fixed bug in parser to not allow module to be parsed more than once.
- Fixed bug that lead to an assertion error (see instance6.1.v for test case).
- Fixing bug with calculating list and concatenation lengths when MBIT_SEL
expressions were included.
- Changed Covered's handling of -y directories. Before, all files in these directories
were fed into the parser to look for missing modules. Now, when a module is needed,
the module name is used to find the matching filename in the -y list (basically,
the -y option works like the -y option in Icarus Verilog and VCS). This fix really
streamlined the parsing phase and fixed several bugs.
- Memory declarations are now properly ignored (produced segmentation fault previously).
- Fixed report command to display all lines and expressions in order according to
their line number (the problem is REALLY fixed now).
- Removed hierarchical references from being scored.
All in all, you should notice a huge improvement in the parsing speed, syntax errors are
reported better, more Verilog syntax should be handled properly, the score command will
run a bit faster than before, and the reports should be a bit easier to read. Segmentation
faults and assertion errors should become lesser in number (if not gone altogether?).
I am feeling pretty confident that we are getting close to a stable release as I have
been able to generate a CDD file for a chip that is millions of gates in size (CDD file
was created in the range of 30 - 45 seconds!) Keep the bug reports coming. I have some
things to work on for next release already.
This is the first packaged (in pkgsrc) snapshot after the verilog-0.7
release.
This snapshot adds preliminary support for real variables to the language
to the features already found in verilog-0.7.
Many improvements such as support for mixed dielectric systems and several
bitmap generators for common structures to allow quick application of the
tool. Several bug fixes as well. Voltages outside a shield are set to zero
which fixes a reported result in older versions. Many other improvemnts
and bug fixes are listed in the ChangeLog in the distfile.
have it be automatically included by bsd.pkg.mk if USE_PKGINSTALL is set
to "YES". This enforces the requirement that bsd.pkg.install.mk be
included at the end of a package Makefile. Idea suggested by Julio M.
Merino Vidal <jmmv at menta.net>.
This release represents many bug fixes, expanded language coverage,
greatly enhanced xilinx fpga synthesis and several performance enhancements.
The complete list is rather long.
GDSreader - simple Calma (GDSii) parser/printer tool.
This software has as target the printing/plotting/displaying of Calma (GDSii)
files without using true layout editors. I had once to visualize an unknown
Calma file and customizing LEdit or Magic (the two layout editors I had access
to) was so difficult that I decided to write this program.
Current status:
- gdsreader is in an alpha stage and you should not expect too much from it;
- the Calma files are almost completely parsed (had no layout example that
makes use of BOX/NODE elements);
- given a Calma structure name, a PostScript file and a HPGL/2 file are
generated. The way each layer is handled is controlled by an ASCII
configuration file. The properties that can be set are color, fill (only
solid is supported), hatch (simple or cross, the angle and spacing are user
customizable too).
In order to produce an useful PostScript output, you need to write a
configuration file (default is .layers.config). The one you'll find with the
distribution is suitable for the Calma example test.gds (an actual Bandgap
reference).
This represents many many improvements and bug fixes. A few items to
note are that the attributes used by the symbol library have been
greately cleaned up and unified. You may want to run gsymupdate and gschemupdate
if migrating from older versions of the tools.
This is a development snapshot. Packages of the released/stable
versions will be imported as 'cad/covered' when available.
Covered is a Verilog code coverage analysis tool that can be useful
for determining how well a diagnostic test suite is covering the
design under test. Typically in the design verification work flow, a
design verification engineer will develop a self-checking test suite
to verify design elements/functions specified by a design's
specification document. When the test suite contains all of the tests
required by the design specification, the test writer may be asking
him/herself, "How much logic in the design is actually being
exercised?", "Does my test suite cover all of the logic under test?",
and "Am I done writing tests for the logic?". When the design
verification gets to this point, it is often useful to get some
metrics for determining logic coverage. This is where a code coverage
utility, such as Covered, is very useful.
Please note that this package is a development snapshot and while it
contains the latest and greatest features, it may be buggy as well.
There is a seperate package which is made of the stable releases.
Changes since last version:
* fixed bug which caused huge memory usage and crashing when zooming way
in to a layout
* Two bugs in aperture macros fixed; one caused "multi macro" macros not
to work properly and the other was related to primitive 20.
* The Debian build system discovered that I checked if unsigned were -1.
* Some cleanup/speedup when parsing Gerber by removing nested strncmp's
with a switch/case.
* RS274D caused segfault.
* If %SR%, %SF% and %AS% are defined to their default values the compiler
doesn't complain anymore. I still don't handle them if they are non
default values.
* In some strange corner case we managed to sometimes get spurious lines
showing up on the image.
* Strange drill files from Orcad386 handled better (we all know what Pitch
thinks about Orcad:-) ).
* Dino Ghilardi has contributed some code to be able to set the scale
explicitly. That can be used when printing PNG's generated by gerbv.
He has also written a text on how to actually get them out on the printer.
It is in doc/PNG-print/PNGPrintMiniHowto.txt.
* Round off when converting from inches to pixels changed so poured areas
built up by several lines now seems to fill. Before the change you could,
at certain zoom levels, see gaps that wasn't there.
jmmv at menta dot net.
TkGate is a digital circuit editor and simulator with a Tcl/Tk based
interface. TkGate includes a large number of built-in devices
including basic gates, memories, ttys and modules for hierarchical
design. The simulator can be controlled either interactively or
through a simulation script. Memory contents can be loaded from
files, and a microcode/macrocode compiler (gmac) is included to create
tkgate memory files from a high-level description. The simulator
supports continous simulation, single step simulation (by clock or
epoch) and breakpoints. Save files are in a Verilog-like format.
TkGate also includes a number of tutorial and example circuits which
can be loaded through the "Help" menu. The examples range from a
simple gate-level 3-bit adder to a 16-bit CPU programmed to play the
"Animals" game.
TkGate has a multi-langauge interface with support for English,
Japanese, French and Spanish.
Release Notes for Icarus Verilog Snapshot 20021019
The synthesizer now detects asynchronous set/reset inputs to DFF
devices. The fpga and vvp code generators have been updated to support
these signals.
The vvp code generator also gained some register management code that
improves the thread register usage. This redoces code size for certain
common cases, and thus improves simulation performance.
The requirements on `ifdef and related compiler directives has been
relaxed, to correspond to more common behavior.
The parameter range support crashed if the range expressions had
parameters in them. This is fixed, and some signed-ness bugs fixed
along with it.
Rearrange some of the configure script tests to assure better
compatibility accross platforms.
Yet another bunch of bugs in different corner cases of Gerber files
has been fixed. Many fixes in polygon area fill, some fixes in calculating
circles, a statically allocated array caused strange stray segfaults when
drawing aperture macros.
A bunch of new command line switches. Most important are:
* --display: use as in all other X-programs, ie open window from a remote
computer.
* --geometry: Sets the geometry. Usually gerbv guess the resolution of
your window and sets the window size accordingly. If you for instance
have a bigger virtual window than actual screen the window can get quite
big. With this switch you can override with for example --geometry=400x300
Fixes in drill file parser. Many drill files don't have drill sizes in them,
else perfectly valid files. Pitch fix makes gerbv parse drill files even
though they don't have drill sizes defined, but under protest.
Greatest fix of them all. Super imposing. Handles paint-scratch-paint
more proper. Changed dramatically how different layers are drawn "on
top of each other".
Changes in Dinotrace 9.1h 08/30/2002
*** Save_duplicates is now on by default.
**** Fixed several bugs when save_duplicates is enabled.
**** Updated Windows install. [Greg Loxtercamp]
**** Fixed coredump reading wide ascii traces. [Vitaly Oratovsky]
Release Notes for Snapshot 20020828
This snapshot adds support for parameter and localparam bit
ranges. This is a IEEE1364-2001 feature, although some -1995 compilers
have supported it in the past.
Fixed a *nasty* and slippery bug with the evaluation of bit select of
nets. (Bit select of variables was unaffected.) The symptoms did not
clearly point to the problem, so bugs related to it were often mis-
reported.
Gate delays were lost when constants were propagated to their
inputs. This is fixed for the known broken cases. Also, mux output
delays have been fixed. Also, release statements that apply to elided
nets are turned into no-ops.
The r-values of non-blocking assignments are now precalculated at
compile time, if possible, as is done with blocking assignments. This
speeds up constant propagation, and is more thorough.
Also optimize subtraction of small constants from vectors, with the
new %subi instruction in vvp. This saves some in code size and thread
footprint.
Handling of x in r-value bit selects and memory word selects did the
wrong thing. Now they do the right thing. Also, x in the selector of
?: ternary operators does the right (and complicated) thing now. In
the process, a fork-join code generator bug was fixed.
Several bugs with time formatting have been fixed.
Temporaries in sequential blocks are detected by the synthesizer, and
converted into wires when needed. This expands support for
combinational logic synthesis.
and if that doesn't exist look for /usr/libexec/cpp0. While here,
use ${X11BASE}/include instead of /usr/X11R6/include.
Should fix recently noted bulk build problems on 1.6 systems.
bug fixes: A couple of apertures drawn wrong has been fixed, like
lines with square apertures and rotation of aperture macro primitive 4.
new features: Zoom outline and the measurement tools. You can also export
the image as PNG,
Remove `-p' from mkdir arguments, it is already part of ${MKDIR}.
While here substitute a couple of ${PREFIX} by `%D' in
`@exec ${MKDIR} ...' lines and add a couple of missing `%D' in such lines too!
files. In addition sinclude the files 'site-config.inc',
'user-config.inc', and 'proj-config.inc' to allow for per-site, per-user,
and per-project configuration instead of only per-site configuration.
This is essential for use by non-sysadmin users and users who need to
keep project specific setups.
- remove all compiler warnings on alpha
- add ${PKG_SYSCONFDIR}/pcb/local.inc where admins can list site specific
libraries to be included instead of modifying one of the regularly
installed/deinstalled files. This way a local config is preserved when
the pkg is upgraded. Also a local config can be applied without modifying
one of the files which is checksummed during the install.
points to the magic installation. This avoids possible conflicts with
some other UCB tools which use CAD_HOME. Noted in private email from
Daniel Senderowitz.
Graphical quirks fixed are:
- zooming around the mouse pointer.
- zooming several steps at once goes much faster. No calculation and
redrawing in each zoom step, but in the last step.
When you click with the left mouse button on a layer button you
get a popup menu with color selection, load file and unload file.
That is on a "per layer-basis". The "global" "Open File..." menu is
removed in favor for this.
many improvements and bug fixes since the last packaged snapshot including:
-added the $sizeof system function as a builtin
-In VPI, the simulator event callbacks now work
-Concatenation expressions in parameters were broken are broken
-added the vpiModule iterator to VPI scope handles
Magic is an interactive system for creating and modifying VLSI circuit
layouts. With Magic, you use a color graphics display and a mouse or
graphics tablet to design basic cells and to combine them
hierarchically into large structures. Magic is different from other
layout editors you may have used. The most important difference is
that Magic is more than just a color painting tool: it understands
quite a bit about the nature of circuits and uses this information to
provide you with additional operations. For example, Magic has
built-in knowledge of layout rules; as you are editing, it
continuously checks for rule violations. Magic also knows about
connectivity and transistors, and contains a built-in hierarchical
circuit extractor. Magic also has a plow operation that
you can use to stretch or compact cells. Lastly, Magic has routing
tools that you can use to make the global interconnections in your
circuits.
Magic is based on the Mead-Conway style of design. This means that it
uses simplified design rules and circuit structures. The
simplifications make it easier for you to design circuits and permit
Magic to provide powerful assistance that would not be possible
otherwise. However, they result in slightly less dense circuits than
you could get with more complex rules and structures. For example,
Magic permits only Manhattan designs (those whose edges are vertical
or horizontal).
The most significant changes are the BJT model and "binning".
New features:
1. BJT model.
2. "Binning" for all MOS models.
3. Internal element: non-quasi-static poly-capacitor. (needed by BJT).
4. Enhancements to the data structures and model compiler to support
binning in general.
5. A line prefixed by "*>" is not ignored, in spite of the fact that
"*" usually begins a comment. This is a deliberate incompatibility
with Spice. If you prefix a line by "*>" it will be interpreted as a
non-comment in Gnucap, but a comment in Spice.
6. Circuit line prefixes of ">" and command prefixes of "-->" are
ignored. This is so you can copy and paste whole lines, without
having to manually remove the prompt string.
Changes that may or may not be improvements.
1. It is not the default to include stray resistance in device models.
The option "norstray" will revert to the old behavior. This is only a
change to the default value of "rstray".
Significant internal changes:
1. The internal element non-quasi-static poly-capacitor actually
works. It is used by the BJT model, and will eventually be used by
MOSFET models.
2. There are now two poly_g devices: "CPOLY_G" and "FPOLY_G". There
are interface differences that impact modeling. Previously, there was
only one, which is equivalent to the "FPOLY_G".
Release Notes for snapshot 20020317
The first difference in this snapshot from the 0.6 release is that vvm
is no longer compiled by default. If you want to compile vvm, you must
enable it at configure time (--enable-vvm) and rebuild from
scratch. Eventually, vvm will disappear from the release altogether.
The next major difference is new support for user defined
functions. It is new support, so it is bound to be buggy, but it
should be somewhat complete. The major problem has been solved, so all
that remains are bugs around the edges.
The vvp run-time scheduler has been changed slightly. The run time
behavior is getting increasingly precise and picky, as larger designs
are thrown at the compiler. The change introduced in this snapshot
fixes logic gates to not propagate zero-time pulses, and thus fixes
some weird bugs in large designs.
I've also added initial support for the Verilog 200x pragma comment,
which are (* *) pairs. For now, the compiler ignores them as
comments. This is what a compiler is supposed to do with anything that
is not specifically recognized.
Also, Tony (Anthony Bybell) has added LXT dump support. The LXT output
file is a waveform output format that is much more compact then VCD.
The gtkwave waveform viewer supports the LXT format, and should
operate a bit faster when viewing LXT files. For now, there are
separate system tasks for managing LXT output ($lxt_dumpvars, etc) but
eventually the dump format will be selectable by environment variable
or command line switch.
This snapshot also includes various random bug fixes and improved
error messages for incorrect code.
