Release Notes for Icarus Verilog Snapshot 20041004
Some minor Makefile bugs have been fixed, and source file text
formatting has in some cases been normalized for release. Also,
configure scripts have been factored for a more consistent build.
Fixed continuous assignments to carry strength when needed for correct
behavior. This bug led to subtly incorrect reset behavior, but could
have caused strength modeling errors in a variety of situations.
Fixed some <= vs >= behaviors to be consistent. The results of these
comparisons, when sized values are involved, are more standard now.
in the process. (More information on tech-pkg.)
Bump PKGREVISION and BUILDLINK_DEPENDS of all packages using libtool and
installing .la files.
Bump PKGREVISION (only) of all packages depending directly on the above
via a buildlink3 include.
The big news is that module instance arrays now work. Gate and UDP
instance arrays have worked for a while, but module instance arrays
were more tricky because of the scope arrys they create. The issues
have been dealt with, and module instance arrays are now supported.
An interesting but subtle set of bugs in the evaluation of ternary
expressions has been fixed. The problems expressed themselves when the
condition expression was constant.
Degenerate wait statements now work properly.
The @* syntax apparently missed sensitivities in l-value expressions
of assignment statements. This led to subtle bugs in carefully crafted
bits of code.
Verilog attributes are properly parsed in a few more contexts. Also,
some specify syntax cases have been fixed.
Some minor spelling and documentation errors have been fixed, along
with assorted compiler warnings.
changes include:
Added support for the `default_nettype directine, including the
default net type of "none", which turns off implicit net declarations.
Signed /, % and >>> in nets should now work properly. Also, various
operators of all sorts applied to constants have been improved.
Ranges now work on localparams.
Added the system tasks $unsigned, $is_signed, $mti_random and
$mti-dist_uniform. See the make README.txt for a description of these
system functions. Also, flesh out the standard random number
generators to match the sequences generated by other compilers.
There is now an "sft" file that describes to the compiler the return
value of system functions. This allows user supplied system functions
to have interesting return types. See "SYSTEM FUNCTIO TABLE FILES" in
the iverilog man page. Include a sft file for the system functions,
and move the system functions over to that mechinism.
Fix the behavior of $fgets in tight fitting result buffers.
A variety of compilation environment fixes have been added. These
involve configure scripts and Makefiles.
And of course a variety of other bug fixes, and so on and so forth.
* Release Notes for Icarus Verilog Snapshot 20040606
Ports of primitives can bind by name as well as by position. Also
support Verilog 2001 style port declarations for primitives.
System function return types can now be specified by system function
table files. System Function Table Files are described in the iverilog
man page. Also include better system function return types in VPI.
Non-blocking assign of real values to real variables now works.
Properly handle nul strings ("") as 8bit values. This is a weirdness
legacy of XL.
Fix some synthesis problems for logical OR and logical AND. Bitwise OR
and AND were fine. These fixes affected simulation as well.
Handle wait statements with all sorts of constant values. These are
sometimes weird, bug legal.
Handle Negative value reals, and a few other bugs related to real
numbers.
Change internal use of identifiers to perm_strings for better
performance.
Functions returning unsupported types now generate error
messages. Previously, they would quietly generate bad
code. Infrastructure is also added to eventually support arbitrary
function return types.
Better compile-time support for Cygwin vs mingw32.
The ipal target is removed from this source. (ipal is now an add-on
package that is compiled seperately.)
There was a couple of snapshots since february; besides bugfixes the
major highligths might be:
-handling of real values at various places
-support for library modules (esp cadence PLI1)
-better FPGA support (esp Virtex II)
-"vvp" interactive mode added
Also converted to buildlink2, and dependencies to libz, libbz2 and
readline added.
This is the first packaged (in pkgsrc) snapshot after the verilog-0.7
release.
This snapshot adds preliminary support for real variables to the language
to the features already found in verilog-0.7.
Release Notes for Icarus Verilog Snapshot 20021019
The synthesizer now detects asynchronous set/reset inputs to DFF
devices. The fpga and vvp code generators have been updated to support
these signals.
The vvp code generator also gained some register management code that
improves the thread register usage. This redoces code size for certain
common cases, and thus improves simulation performance.
The requirements on `ifdef and related compiler directives has been
relaxed, to correspond to more common behavior.
The parameter range support crashed if the range expressions had
parameters in them. This is fixed, and some signed-ness bugs fixed
along with it.
Rearrange some of the configure script tests to assure better
compatibility accross platforms.
Release Notes for Snapshot 20020828
This snapshot adds support for parameter and localparam bit
ranges. This is a IEEE1364-2001 feature, although some -1995 compilers
have supported it in the past.
Fixed a *nasty* and slippery bug with the evaluation of bit select of
nets. (Bit select of variables was unaffected.) The symptoms did not
clearly point to the problem, so bugs related to it were often mis-
reported.
Gate delays were lost when constants were propagated to their
inputs. This is fixed for the known broken cases. Also, mux output
delays have been fixed. Also, release statements that apply to elided
nets are turned into no-ops.
The r-values of non-blocking assignments are now precalculated at
compile time, if possible, as is done with blocking assignments. This
speeds up constant propagation, and is more thorough.
Also optimize subtraction of small constants from vectors, with the
new %subi instruction in vvp. This saves some in code size and thread
footprint.
Handling of x in r-value bit selects and memory word selects did the
wrong thing. Now they do the right thing. Also, x in the selector of
?: ternary operators does the right (and complicated) thing now. In
the process, a fork-join code generator bug was fixed.
Several bugs with time formatting have been fixed.
Temporaries in sequential blocks are detected by the synthesizer, and
converted into wires when needed. This expands support for
combinational logic synthesis.
many improvements and bug fixes since the last packaged snapshot including:
-added the $sizeof system function as a builtin
-In VPI, the simulator event callbacks now work
-Concatenation expressions in parameters were broken are broken
-added the vpiModule iterator to VPI scope handles
Release Notes for snapshot 20020317
The first difference in this snapshot from the 0.6 release is that vvm
is no longer compiled by default. If you want to compile vvm, you must
enable it at configure time (--enable-vvm) and rebuild from
scratch. Eventually, vvm will disappear from the release altogether.
The next major difference is new support for user defined
functions. It is new support, so it is bound to be buggy, but it
should be somewhat complete. The major problem has been solved, so all
that remains are bugs around the edges.
The vvp run-time scheduler has been changed slightly. The run time
behavior is getting increasingly precise and picky, as larger designs
are thrown at the compiler. The change introduced in this snapshot
fixes logic gates to not propagate zero-time pulses, and thus fixes
some weird bugs in large designs.
I've also added initial support for the Verilog 200x pragma comment,
which are (* *) pairs. For now, the compiler ignores them as
comments. This is what a compiler is supposed to do with anything that
is not specifically recognized.
Also, Tony (Anthony Bybell) has added LXT dump support. The LXT output
file is a waveform output format that is much more compact then VCD.
The gtkwave waveform viewer supports the LXT format, and should
operate a bit faster when viewing LXT files. For now, there are
separate system tasks for managing LXT output ($lxt_dumpvars, etc) but
eventually the dump format will be selectable by environment variable
or command line switch.
This snapshot also includes various random bug fixes and improved
error messages for incorrect code.
many many changes since the last packaged snapshot.
A brief sampling of the changes (which include many bug fixes and
enhancements) is:
A variety of little problems with $display format strings have been
fixed.
The % operand should now simulate properly. Also, the * operator is a
little bit more optimized, and works in constant expressions.
Several bugs in strength modeling have been fixed. This includes drive
strengths on continuous assignments, which in the past generated code
without the strengths. Also, vvp gained some missing support for
constants with strength. I think that strength modeling is now
complete.
vpi_get_vlog_info support has been added to the vvp run-time. This is
a PLI function that allows access to run-time command flags. Also, vpi
access to root modules now works properly.
Many changes since the last packaged snapshot. A sampling of these are:
Support for hierarchical names has been largely rewritten. The major
consequence of this is that escaped names now have much better
support. By now, most any combination of escaped and hierarchical name
should work properly, for nets, parameters, and anything else.
Output delays for primitive gates, including user defined primitivies,
should now work properly. Delays on nets still do not work, although
the parser now parses them and prints a "sorry" message.
Bugs in support for division(/) and modulus (%) have been fixed.
Bugs in l-values of synthesized DFF devices have been fixed. These
bugs were related to part selects of vectors in l-values.
A few XNF code generator bugs and limitations were fixed.
And as usual, a variety of miscellaneous bugs have been fixed in this
snapshot.
The bit size of the results of some unary redunction operators is now
properly handled. Also, similar problems with logical functions have
been fixed.
force/release now works for variables, though not yet for
nets. Assign/deassign already work.
many other bugfixes
changes since last snapshot include:
- addition of a fpga target for synthesis. outputs edif, optimized for
xilinx virtex parts.
- fixed bug with synthesis of !=
- fixed bug in hex constant parsing
- fixed vvp bug with subtracting very wide words
- much improved VCD output
- many other bug fixes and robustness improvements.
foo-* to foo-[0-9]*. This is to cause the dependencies to match only the
packages whose base package name is "foo", and not those named "foo-bar".
A concrete example is p5-Net-* matching p5-Net-DNS as well as p5-Net. Also
change dependency examples in Packages.txt to reflect this.
changes are:
-----------
RELEASE NOTE FOR ICARUS VERILOG 20010630
I've done some cleanup of the mingw port of Icarus Verilog. I've also
added instructions for how to build Icarus Verilog under mingw. I'm
working on making that the preferred way to support Windows, and when
I make the 0.5 release I will make Windows binaries this way. Anyhow,
feedback on the build instructions and the build results using the
instructions in mingw.txt are welcome.
I've make "vvp" the default target type. The older vvm behavior is
available with the "-tvvm" flag to iverilog, but I would rather be
told about (and fix) bugs in the vvp code generator and run time.
I've added support for the (unsigned) right shift operator. The left
shift has been working for a while now, but right shift somehow
slipped through the cracks. The shift operators still don't quite work
in structural contexts, but they should show up sometime next week.
I've finally got VCD output working properly with vvp. It may even be
better then with vvm, although some internal symbols are still generated.
A few odd bugs have been fixed, including a code generation error for
xnf, and error checking of user defined function parameters.
many changes since the last snapshot. Mostly they involve expanded
VVP support. The VVP target now passes >200 of the tests from the
test suite. While not as complete as the VVM target, VVP is getting
closer and its _much_ _much_ faster.
Changes since the last packaged snapshot from the authors announcements:
Icarus Verilog snapshot 20010422
--------------------------------
I've integrated a bunch of UDP patches from Stephan Boettcher. These
go to the core of ivl, so if you use Icarus Verilog with UDPs, you
might want to give this a test for us.
Stephan has also added some ivl_target support for UDP devices. This is a
prerequisite to vvp support for UDP devices.
Some of you have been beating me over the head about disable, so the
vvp target now supports disable. It only works in certain very constrained
situations, but the idea is there and the more common cases are simply a
matter of getting around to them. I actually could use more examples of
the use of disable for the test suite.
In the process, I have settled on the interaction of threads and scopes,
and changed the %fork syntax to match. See the README.txt and opcodes.txt
file for details. The implementation of %end and %join simplified in
the process.
The vvp-tgt code generator supports a few more gate types. New gate
types are pretty easy to add, it's just boring grunt work. That's why
they've been popping up slowly.
I've also got certain behavioral shifts working. Only constant shifts,
so far, but this covers a pretty large percentage of the real world
uses of shift, I think.
I fixed a few specify block parse problems, so it should ignore
even more complex specify blocks now:-) One of these days I really will
properly support specify blocks.
PROGRESS
I was hoping to get vvp up to a similar level as vvm by the end of
April, but that doesn't look like it's going to happen. I'm up to 182
tests passed, compared to 318 of Icarus Verilog/vvm, so I have a ways
to go yet. I see no real point to making a release until I get up to
300 or so tests passed. That is the goal for 0.5 release.
But of course if vvp is enough for you, then it is soooo much faster
then vvm.
Icarus Verilog 20010415 Snapshot
--------------------------------
As with all the most recent snapshots, this is almost entirely progress
with the vvp code generator and simulation engine. I'm up to 159 tests
passed in the test suite, so I'm getting there. But there's still plenty
to go.
I also fixed what appeared to be a minor problem with elaboration of ?:
expressions in continuous assignments. The code was actually fine, it
was a spurious assert. This fix affects vvm as well.
Icarus Verilog/vvp now support <= statemements with internal delays.
That is, "foo <= #10 bar;" should work properly, and there are tests
in the suite that prove it. This is a pretty common syntax, so this
should help a lot of folks.
I also fixed a bug in the code generator that would cause it to put a
constant bit as a destination for the bitwise boolean operators. This
caused run-time asserts.
The event or support in vvp has been extended to now support arbitrary
width, so now you can for example wit for any changes in a 32bit reg.
This handles most of the likely cases, so @ statements should now be
pretty generally functional.
The handling of run-time threads has been revamped in preparation for
support of the disable statement. It also plugs a memory leak where
fork/join and task/function calls are invoked. And this version should
also clean up all those tiny initial foo=bar threads that all programs
seem to have. Threads that are done are now freed, along with their
memory, hopefully reducing the runtime memory footprint.
That's pretty much it this time 'round. Working with threads took some
time, so the progress isn't as flashy as it sometimes is.
There is still lots to do with vvp before 0.5, but I would appreciate
any feedback you can offer. It's complete enough already that I'm able
to accept bug reports on it, even if it turns out to be a "not supported
yet" type of thing. At this point, I'd be curious to know what hangups
are preventing its regular use.
changes since last snapshot are (from the authors email)
verilog-20010407
--------------------
Still more progress on the new VVP simulation engine:
As with last week, this snapshot includes a lot of work on the ivl_target
API in support of code generation for vvp. Also, the vvp execution engine
has progressed some.
In fact, vvp has grown up to understand signed vectors and some signed
expressions. The signed vectors are mostly for VPI use, the signed
comparison instructions actually do signed work. Case comparisons are
new, along with %and and %or instructions, and %nor/r for reduction.
I also added a few new gate types to the .functor support.
A bug in the propagation of values by %set instructions has been fixed.
Specifically, the %set instruction not only sets the value of the .var
that it references, but also executes the propagation events that result.
This fixed some event ordering bugs.
Some VPI support needed by system.vpi is added to vvp to allow it to
properly handle signed signals, decimal values, and a few other details.
$display should work much better then it did last week.
Back in the vvp.tgt code generator, lots of new stuff is happening.
Several of the bitwise binary operators have been added, as well as
more comparison operators. This includes handling of signed expressions.
This also implies that vvp.tgt generates the proper .net vs .net/s
and .var vs .var/s statements.
User defined functions and tasks are now working. In fact, the vvp
target probably handles more functions (in behavioral code) then the
vvm engine. I've received several bug reports about user defined functions
with loops, that don't work under vvm. These should work with vvp.
Non-blocking assignments now work, too.
All forms of case/casex/casez are supported by the code generator, and
use the proper compare instructions. Forever, Repeat and While loops
also work now. A few bugs in event handling, and all the edge types
(including behavioral triggers) should work with limitations. Event or
is still in the works, and any-edge of large vectors (>4 bits) does not
work.
*Whew!*
As you can see, a *lot* of stuff is happening. I'm up to passing 110+
tests in the regression test suite (Icarus Verilog/vvm passes 318 tests)
so the changes are actually making things work. Test and be merry!
verilog-20010331
--------------------
More and more progress on VVP. More and more snapshots.
A lot of work has been done to the ivl_target loadable target API.
This API is growing to support the also growing tgt-vvp target. I've
added support for case statements, event triggers fork blocks.
Of course this also means that the tgt-vvp code generator and the
vvp simulator now support constructs including case, events, and
parallel blocks.
I've also fixed up the driver to properly report errors that tgt-vvp
detect. This makes the test suite regression script work a lot better.
I'm up to more then 70 tests in the test suite passing. I'm finding
that writing the code generator for vvp assembly is a *lot* easier
then writing a code generator for C++/vvm. Fortunately, the vvp
assembler is pretty fast.
At any rate, the vvp simulation engine is starting to show signs of
being useful. It still does not cover nearly as much of Verilog as
vvm, but what it does cover is so much faster that it may be worth
your while to try it out. And more eyes looking at it can only be a
good thing.
the authors announcement are:
There are a few bugs in the main compiler that are fixed. There has
also been an extension to the $fopen that adds support for opening
files for reading. The $fgetc has been added to take advantage of this.
This was done on the VPI side, although a slight extension to the mcd
functions was created.
The real news is the vvp simulation engine. I've added the tgt-vvp
code generator source and the vvp assembler/simulator, and the combination
actually produces the occasional working program. And it makes them
very quickly. So far as I can tell now, I am going to be very pleased
with the final outcome when this work is complete. However, it is not
at all ready to use. This snapshot is mostly to give a preview of things
to come to a wider audience.
HOW VVP WORKS
If you are accustomed to the existing vvm behavior, you remember that
the vvm simulator works by generating C++ and feeding that to the g++
compiler. Many of you are painfully aware of that.
VVP does *not* work like that. Instead of generating C++, the
generator emits assembly language for an abstract simulator processor.
The processor that the assembly targets doesn't really exist, but the
vvp program, included in this Icarus Verilog snapshot, assembles the
code to data structures in memory, then efficiently emulates the abstract
processor.
So the simulation of a program via vvp works by first compiling the
Verilog to vvp assembly. The vvp.tgt modules generates the code, and
is envoked when you use the ``-tvvp'' switch to iverilog.
The vvp assembly file so created is then passed to the vvp program to
be assembled and executed. There is a single vvp input file that is the
design to simulate. The vvp assembler is designed to execute the design
efficiently.
HOW TO LEARN MORE
The ivl_target.h header file describes the loadable target API that
the vvp code generator uses to gain access to the design. Then the
tgt-vvp directory contains the implementation of the vvp code generator.
The vvp directory contains the implementation of the assembler/simulator
that runs the compiled design. The README.txt file describes how the
vvp program works in general, and points to other txt files. There are
a variety of other .txt files in the vvp directory that describe how
the major components of the vvp program work.
first component is now a package name+version/pattern, no more
executable/patchname/whatnot.
While there, introduce BUILD_USES_MSGFMT as shorthand to pull in
devel/gettext unless /usr/bin/msgfmt exists (i.e. on post-1.5 -current).
Patch by Alistair Crooks <agc@netbsd.org>
