Unfortunately, guile{,14}/buildlink3.mk directly includes it, and I don't
know which dependencies actually need libltdl, so it was a recursive bump.
Hopefully this recursive inclusion can be ripped out of
guile{,14}/buildlink3.mk at some point and bubble down to dependencies that
actually use libltdl, avoiding this headache in the future....
The current release is a considerable improvement over the previous stable
release. It includes 20 months of fixes and language coverage improvements.
For a complete history of changes, see the release notes for individual
snapshots between the 0.7 and 0.8 releases found at
ftp://ftp.icarus.com/pub/eda/verilog/snapshots/pre-0.8
A brief list of highlights:
- Support for advanced standard data types such as real,
- Lots more language support in general,
- Kernel of an extensible, interactive debugger is new,
- More complete support for user supplied system functions and tasks,
including PLI system functions with various return value types,
- Better standards compliance for core system tasks and functions in
general, including some Verilog 2001 file I/O support, and
- Performance improvements in general.
in the process. (More information on tech-pkg.)
Bump PKGREVISION and BUILDLINK_DEPENDS of all packages using libtool and
installing .la files.
Bump PKGREVISION (only) of all packages depending directly on the above
via a buildlink3 include.
gsmc is a GTK application that allow to do all the calculation
usually done on a Smith Chart. It permits to make calculation
for network composed by resistor, capacitor, inductance, and
transmission line (also as stub). Network topology is
limited to series, parallel and as trasmissive
for trasmission line. No series connection are allowed in parallel
branch, neither parallel connection in series branch.
Trasmission line can be placed as quadrupole or as a parallel or
series stub, either opened or shorted at the other end.
Calculation procedure starts with setting the initial impedance to be
matched, next network elements are added and tuned to obtain the
desidered impedance value.
The network so obtained can be saved in spice format for other analysis;
current work can be saved for succesive retrieve.
The initial (start) impedance is thought as "the load" so when
adding a trasmission line placed as a quadrupole rotation is
clockwise, going "toward generator"; generator is placed after the
last network element, as can be seen from spice output.
TNT-MMTL, the Multilayer Multiconductor Transmission Line 2-D and 2.5-D
electromagnetic modeling tool suite, generates transmission parameters
and SPICE models from descriptions of electronics interconnect
dimensions and materials properties.
MMTL programs and supporting libraries and documentation have been
under development at the Mayo Clinic since the mid-1980s. The programs
were developed under government sponsored electronics research
programs in the Special Purpose Processor Development Group
(SPPDG). They have been employed extensively at Mayo and distributed
to some government agencies and research collaborators. At the
beginning of 2004, we decided to release the TNT graphical front-end
and MMTL programs as free software under the GNU General Public
License (GPL). Technically, MMTL programs are in the class of 2-D and
2.5-D "field solvers", which convert dimensions and materials
properties into electronic design parameters. The MMTL suite consists
of several programs, including lossy, loss-free, quasi-static, and
full-wave simulators. Circuit parameters are computed by either the
method of moments (MOM) or finite element methods (FEM). Basic
per-unit-length parameters are generated by the simulator, and can be
converted into HSPICE W-element models. MMTL is similar in many ways
to commercial field solver products which typically cost thousands of
dollars.
All library names listed by *.la files no longer need to be listed
in the PLIST, e.g., instead of:
lib/libfoo.a
lib/libfoo.la
lib/libfoo.so
lib/libfoo.so.0
lib/libfoo.so.0.1
one simply needs:
lib/libfoo.la
and bsd.pkg.mk will automatically ensure that the additional library
names are listed in the installed package +CONTENTS file.
Also make LIBTOOLIZE_PLIST default to "yes".
The big news is that module instance arrays now work. Gate and UDP
instance arrays have worked for a while, but module instance arrays
were more tricky because of the scope arrys they create. The issues
have been dealt with, and module instance arrays are now supported.
An interesting but subtle set of bugs in the evaluation of ternary
expressions has been fixed. The problems expressed themselves when the
condition expression was constant.
Degenerate wait statements now work properly.
The @* syntax apparently missed sensitivities in l-value expressions
of assignment statements. This led to subtle bugs in carefully crafted
bits of code.
Verilog attributes are properly parsed in a few more contexts. Also,
some specify syntax cases have been fixed.
Some minor spelling and documentation errors have been fixed, along
with assorted compiler warnings.
- distfile has moved
- license has changed. Patches are the result of de-fuzzing the
old patches since the new source files have the new (less restrictive)
license.
========================================================================
Release Notes for PCB snapshot 20040903
========================================================================
- enable -Wall when compiling with gcc. Many compiler warnings have
been fixed.
- add a short man page which refers the user to the real documentation
- Added ExecuteFile(file) action which allows the execution of several
actions contained in a text file.
- Added -script <file> flag which specifies a file containing actions
to be executed upon startup.
- Various documentation improvements
- Protect some gcc extensions with tests for gcc. This allows
compilation with the IRIX c compiler.
- Add support for a background image in the drawing area which can
help in importing a layout from a scanned image.
- Updated the ~geda library 150 and 300 mil width SOIC packages
to remove silk on pads and to more closely follow the IPC
recommendations
- Added support for menu accelerators.
- segfault when breaking apart an element with no element selected
bug fixed.
- autorouter improvements
- added more 400mil DIP packages to ~geda library
- fix a trace optimizer bug which produced a segfault
- other various bug fixes
changes include:
Added support for the `default_nettype directine, including the
default net type of "none", which turns off implicit net declarations.
Signed /, % and >>> in nets should now work properly. Also, various
operators of all sorts applied to constants have been improved.
Ranges now work on localparams.
Added the system tasks $unsigned, $is_signed, $mti_random and
$mti-dist_uniform. See the make README.txt for a description of these
system functions. Also, flesh out the standard random number
generators to match the sequences generated by other compilers.
There is now an "sft" file that describes to the compiler the return
value of system functions. This allows user supplied system functions
to have interesting return types. See "SYSTEM FUNCTIO TABLE FILES" in
the iverilog man page. Include a sft file for the system functions,
and move the system functions over to that mechinism.
Fix the behavior of $fgets in tight fitting result buffers.
A variety of compilation environment fixes have been added. These
involve configure scripts and Makefiles.
And of course a variety of other bug fixes, and so on and so forth.
which are the full option names used to set rpath directives for the
linker and the compiler, respectively. In places were we are invoking
the linker, use "${LINKER_RPATH_FLAG} <path>", where the space is
inserted in case the flag is a word, e.g. -rpath. The default values
of *_RPATH_FLAG are set by the compiler/*.mk files, depending on the
compiler that you use. They may be overridden on a ${OPSYS}-specific
basis by setting _OPSYS_LINKER_RPATH_FLAG and _OPSYS_COMPILER_RPATH_FLAG,
respectively. Garbage-collect _OPSYS_RPATH_NAME and _COMPILER_LD_FLAG.
gnetman is a program which currently supports advanced SPICE
netlisting from gschem (part of the gEDA tool suite). The
primary use so far has been for complex IC design. Supported
features include multi-level hierarchy, instance arrays, and
buses. If you're just doing flat designs for PC boards or
smaller SPICE simulations, the usual path is to use the spice-sdb
netlister for gnetlist instead.
The long term goal of gnetman is far greater. Two projects under
consideration include a schematic generator, and a technology
mapping back-end for Icarus Verilog. Basically, gnetman is a
netlist manipulation database well suited for low-level
manipulation of netlists.
library dependencies (caused by the tcl/tk update to 8.4). Use tclConfig.sh
to determine which libraries are really needed. Noted in last kristerw@'s
bulk build.
* Release Notes for Icarus Verilog Snapshot 20040606
Ports of primitives can bind by name as well as by position. Also
support Verilog 2001 style port declarations for primitives.
System function return types can now be specified by system function
table files. System Function Table Files are described in the iverilog
man page. Also include better system function return types in VPI.
Non-blocking assign of real values to real variables now works.
Properly handle nul strings ("") as 8bit values. This is a weirdness
legacy of XL.
Fix some synthesis problems for logical OR and logical AND. Bitwise OR
and AND were fine. These fixes affected simulation as well.
Handle wait statements with all sorts of constant values. These are
sometimes weird, bug legal.
Handle Negative value reals, and a few other bugs related to real
numbers.
Change internal use of identifiers to perm_strings for better
performance.
Functions returning unsupported types now generate error
messages. Previously, they would quietly generate bad
code. Infrastructure is also added to eventually support arbitrary
function return types.
Better compile-time support for Cygwin vs mingw32.
The ipal target is removed from this source. (ipal is now an add-on
package that is compiled seperately.)
========================================================================
Release Notes for PCB snapshot 20040530
========================================================================
This has been an exciting 3 months for PCB. Many improvements have
been made in the program as well as additions and improvements to the
footprint library. Thanks to everyone who has provided feedback,
patches, etc.
----------------------
Additions/Improvements
----------------------
- Expanded DRC checking
- "Realtime" DRC checking
- DRC settings are now stored in the board fle
- Centroid (X-Y) and bill of materials output
- Dynamic menus. Users can now customize the menus via a
site-wide, per-user, or per-project menu resource file.
- Significant improvements to autorouting of congested designs.
- Autorouter can now use power planes.
- Improved appearance in autorouter output.
- Silk on pads/pins is clipped in RS-274-X output
- Ordering is preserved when writing output files so that diff
may be effectively used on pcb files.
- The autoplace feature now actually works
- Added ToggleVisibility action
- Most of the database is now kept in rtrees which avoids linear
searches. This speeds up operation significantly.
- Added SetFlag, ClrFlag, ChangeFlag actions
---------
Bug Fixes
---------
- pin/pad bounding box calculation fixed. Components can
now be placed closer to the edge of the board.
- miter trace optimization bug.
- Fix bug with pins which are enclosed by multiple polygons.
- Shorts to unnamed elements and pins are handled correctly.
- Various memory leaks fixed.
- Fixed some bugs with a really high zoom.
- Fixed default media selection in postscript print dialog
- Fix some DRC bugs with square pins.
------------------
Footprint Library:
------------------
- Added SOJ footprint family (~geda library)
- Added CTS series 742/3/4/5/6 resistor pack footprints (~cts library)
- Added PKG_CONNECTOR_DIL macro to let the HEADER*_1 footprints work
(~geda library)
- Correct the SDIP footprints (~geda library)
- Correct some Minicircuits footprints (~minicircuits library)
- Correct some panasonic footprints (~panasonic library)
- Change refdes silk size for sockets (~johnstech library)
- Increase soldermask relief on some mounting holes
(~johnstech library)
- Convert the COMMON_SMT_DIL_MIL and COMMON_SMT_DIL_MM macros
used by several other libraries to the hi-res format.
- Correct pin count on 100 pin QFP packages (100 not 72)
(~geda library)
- Correct pin count on HEADER60_2 (60 not 50) (~geda library)
additions/changes since gerbv-0.15:
* projects: you can save and load setups in what I call projects.
* GTK+ 2 support
* Now you can invert a layer by the push of button. Basically.
* When gerber files were defined with omit trailing zeros, gerbv could
parse them very bad. Now it should work better.
* Aperture macros did not handle exposures at all. Now they do a better
work. Some thermals are defined from their CAD program as a sequence of
aperture macros instead of just using aperture macro 7. They are drawn
better now.
* Handles tool tables when drawing drill files thanks to Dimitri. See man
page for more info.
by moving the inclusion of buildlink3.mk files outside of the protected
region. This bug would be seen by users that have set PREFER_PKGSRC
or PREFER_NATIVE to non-default values.
BUILDLINK_PACKAGES should be ordered so that for any package in the
list, that package doesn't depend on any packages to the left of it
in the list. This ordering property is used to check for builtin
packages in the correct order. The problem was that including a
buildlink3.mk file for <pkg> correctly ensured that <pkg> was removed
from BUILDLINK_PACKAGES and appended to the end. However, since the
inclusion of any other buildlink3.mk files within that buildlink3.mk
was in a region that was protected against multiple inclusion, those
dependencies weren't also moved to the end of BUILDLINK_PACKAGES.
date. While here bl3ify. Changes are:
Covered-Related NEWS
====================
* 04/11/2004
Release covered-20040210 made. A lot of work has gone into this release to make the report
output more readable and concise. Several bug fixes have been made as well. A GUI is on
the way for report viewing that will be available in alpha version in the next development
release. Below are some of the highlights of this release.
- Added GUI interfacing functions in preparation of upcoming GUI report viewing utility.
- Added more information about expressions to line and combinational logic coverage verbose
information. Rather than just outputting the RHS of the expression, the LHS and assignment
operator (blocking or non-blocking) or IF statement are output to give the user a better
context of the missed logic.
- Fixed bug in param.c where parameters found in the RHS of expressions that were part of
statements being removed were not being properly removed.
- Fixed bug in sim.c where expressions in tree above conditional operator were not being
evaluated if conditional expression was not at the top of tree.
- Changed output of logic in combinational logic verbose coverage reporting to (by default)
use the same format (in terms of endline characters) as the logic was found in the source
code.
- Added '-w [<line_width>]' option to report command that causes combinational logic to be
output to report as much logic as will fit in the value of <line_width> in the report. A
default value of line width is specified internally in Covered to be 105 characters;
however, the user may make this value larger or smaller to suit. This value reverses the
effect of the above bulletin. Added this option to Covered's regression suite to test.
- Completely modified output format of missing combinational logic coverage. Removed a lot
of coverage information that was extraneous. When three or more subexpressions are ANDed,
ORed, logical ANDed, or logical ORed, coverage information is output in a special way to
increase readability/understandability for this coverage.
- Added "GENERAL INFORMATION" section to all reports which specifies general information
about this report (this eliminates a lot of redundant information in the report to improve
readability).
- Added the name of the CDD file from which a report has been generated from in the
GENERAL INFORMATION section of the report.
- When a CDD file is created due to merging CDD files, the names of the original CDD files
are now stored in the merged CDD file. This information is output in the GENERAL
INFORMATION section of the report (created from this merged CDD file) to indicate to the
user this information.
- If a CDD file is created due to merging CDD files and the leading hierarchies in each of
those CDD files are different, a bullet in the GENERAL INFORMATION specifies this and
reminds the user that the leading hierarchy information will not be output in the rest of
the report (instead the string "<NA>" replaces the leading hierarchy information). This
will help to eliminate confusion when viewing the reports and fixes an outstanding bug
in Covered.
- Added starting and ending line information to module structure for GUI purposes.
- Removed scope information in CDD file for expressions, signals and statements. This
information was not used, caused CDD files to become excessive in size and mildly speeds
up reading in CDD files.
- Fixed bugs in combinational logic report section where summary coverage numbers and verbose
coverage numbers did not agree.
- Removed 'c' directory in 'diags' directory and cleaned up Makefile to run regressions.
- Masked off the value of the SET bit in expressions output to CDD files. This information
is not needed and sometimes caused regression failures due to CDD file mismatches on
different platforms or using different simulators.
- Modified regression Makefile to specify the 'vvp' command prior to the compiled VVP
executable when running Icarus Verilog regressions (due to recent change to IV).
- Changed instance-based reports to not merge child instance coverage information into parent
instance coverage information. This is not done in module-based reports, makes reading
this information confusing and doesn't provide us any extra information.
- Fixed bug where modules were being reported in verbose reports when coverage numbers were
100% covered.
- Changed toggle coverage report output to output toggle information in hexidecimal format
versus binary format. This keeps the toggle coverage information more succinct/readable.
Added underlines between every 4th hexidecimal value to help user's to discern the bit
position of a toggle bit.
- Changed the format of the report entirely to enhance readability (many changes here that
the user will immediately see).
- Updated user documentation for new changes and added new section called "Reading the
Report" which will walk the user through several reports and how to interpret the report
information. This section is still in progress at this time.
- Updates to development documentation.
- Lots of new diagnostics added to regression suite. We now have over 200 diagnostics in this
regression.
Special note: Please note that the CDD file format for this release has changed from previous
CDD files and is therefore incompatible with older versions. If you try to read a CDD file
generated from an older version of Covered with the newer version, Covered will tell you that
this cannot be done due to incompatible CDD versions.
* 11/16/2003
Release covered-20031116 made. This development release contains a new way to specify FSMs
within the design by using inline Verilog-2001 attribute syntax. There are also a lot of
bug fixes contained in this release as well as the usual user and development documentation
enhancements. See the list below for more details on the changes made for this release.
- Added better VCD parsing capability to allow bit selects to be "attached" to the signal
names in the VCD variable definition section. The newer versions of Icarus Verilog now
output this format style.
- Added ability to specify FSM location and transition information using Verilog-2001
attributes. Added many diagnostics to regress suite to verify this capability.
- Fixed bug found in stable release that caused an incorrect calculation of unary operations
performed on single-bit values. Fixes bug 835366.
- Fixed bug found in using constant values in the right-hand side of repetitive concatenation
operators. Fixes bug 832730.
- Fixed bugs in reporting of FSM coverage information in the report command.
- Fixed bug in FSM variable binding stage that caused incorrect coverage numbers to be reported
for FSM coverage.
- Fixed bug in handling variables that are too long (more than the allowed 1024 bits). Removes
memory corruption problems when this occurs. Displays warning to user that it has found
a variable that it cannot handle and gracefully disregards any logic that uses these variables.
- Updated user documentation to include new chapter on inline attributes that Covered can
now handle.
- Updated development documentation for new functions added in this release.
* 10/19/2003
Release covered-20031019 made. Lots of modifications to existing structures and supporting
code to increase scoring speed. In my testbenches, I am seeing about a 3-4x improvement
in speed. Additionally, code enhancement for allowing bit selects and signal concatenations
in command-line FSM variable descriptions are now allowed. User documentation has been
updated for these changes. Some bug fixes are also included in this release. The
following list shows the changes from last development release.
- Added ability to parse more complex state "variables". This includes the ability
to specify single and multi-bit signals and the ability to concatenate more than
one signal (or signal bit select) to make a state variable. Please see user
documentation for more information on this.
- Minor tweaks to report format for displaying filenames (only basename of filename
is output instead of the entire path).
- Fixing bug in VCD parser to allow bit select parsing of a variable when the
variable name and bit-select information are not separated by spaces (this is something
that newer versions of Icarus Verilog now does in its VCD files).
- Changed structure for vectors from ints to chars. Each vector element stores information
for one 4-state bit value and its coverage information (instead of storing 4 4-state
variables and coverage information). This reduces memory needed and increases calculation
speed on vectors.
- Fixing bug in signal_from_string function.
- Fixing bug in arc.c related to non-zero LSBs of signals.
- Added new parameter to info line in CDD file that specifies the format of the CDD file.
This is used by Covered to keep CDD files with different formats from being merged, read,
etc.
- Removed LSB information from vector and storing this information in the signal
structure. Reduces memory required, enhances speed, and fixes existing bugs with bit
selects.
- Added more diagnostics to regression suite to test new functionality.
- Updated user documentation for new changes.
* 09/25/2003
Release covered-20030925 made. This release contains the first working FSM code
coverage portion in Covered. There is a lot more to work on in the FSM code coverage
area in the way of automatic FSM extraction and state transition specification, but
this version is able to extract FSM coverage information for an FSM that is located
by the user. Please see user's manual for this release for more details on specifying
FSM location. Summary and verbose reporting are available for FSM coverage at this
point. Additionally, the data format for FSM coverage information in the CDD file
has been finalized. FSM coverage merging is also supported in this release. User and
development documentation has been updated. Please give this development version a
go to get any bugs out of the FSM code coverage engine.
In addition to the FSM coverage support, a bug was fixed in the vector_to_int()
function when converting a vector whose LSB is a non-zero value.
Here is what is on the horizon for FSM coverage that you should expect to see in the
coming development releases.
- Ability for user to specify the location of an FSM using $attribute function.
- Ability for user to specify all possible state transitions for a given FSM on the
command-line and using inline $attribute functions.
- Automatic FSM extraction including locating an FSM and extracting all possible
state transitions.
* 08/20/2003 - Stable Release 0.2.1
Some bugs were found in the covered-0.2 release that needed to be fixed to consider
Covered to be completely stable. This release (covered-0.2.1) contains these fixes
which are outlined below. Please get a hold of this stable release if you have already
downloaded covered-0.2.
- Fixing bug with the initialization of the new symtable structure. Only 255 of the
256 children of each node were being initialized correctly. Fixes a segfault problem with
the symtable_dealloc routine.
- Fixed memory leak problem with file list in parser. This was a long outstanding problem
that has now been understood and fixed.
- Added fclose() after the VCD parsing was complete.
- Fixed a memory problem with the symtable structure that caused other data structure
values to be corrupted.
- Fixed assertion error problem with VCD symbol aliasing.
* 08/16/2003
Stable release covered-0.2 finally made! This release will be the springboard
for adding FSM coverage code, code optimizations as well as a few new features
that should make the score command run much faster. Some important bug fixes
were made in this release and code optimizations have been added to the score
command. If you are getting coverage for a larger design, you should definitely
notice the speed increase. In one of my designs, the speedup was a facter of
a bit more than 3x. The following are the list of changes made for this release.
- Added -ts option to score command to allow the user to see where in the
simulation process the score command is currently at. Please see user
documentation for more details on this new option.
- Fixed bug with multiple wait event statements within same always block.
This means that the CDD files created with the last version of Covered
will be incompatible with the new CDD files.
- Fixed bug with posedge, negedge and anyedge expressions when more than
one of these is found in the same always block.
- Fixed bug in vector comparison function. Vectors will now compare to a value
of true if the values of two vectors (whose bit size is different) are equal
up to the smallest MSB of the two vectors. Before, if two vectors were not
of equal size, a compare would always evaluate to FALSE.
- Removed unnecessary global variables.
- Removed generated development documentation from release and opted to
generate these with a user 'make' in the doc directory (makes release size
smaller and is unnecessary for most users anyways).
- Development documentation updated.
- User documentation and man file updated.
* 08/06/2003
Release covered-0.2pre3 made. It has been quite a while since a release has been made
which has been due to a particularly tricky bug that was found with non-blocking
assignments. This bug generated bad coverage information (this is considered very bad!)
This release contains bug fixes and development documentation updates. If no more problems
are found with this release, I will get the 0.2 release made very soon. The following
is a list of the changes for this release.
- Fixes to line.c and toggle.c to provide better cross-platform support.
- Lots of updates to the development documentation.
- Fixed bug with properly handling hierarchical references in expressions.
- Fixing bug with single-bit parameter handling (caused a diagnostic miscompare
between Linux and Irix OS's).
- Fixed non-blocking assignment bug. This bug affected the order of execution in
Covered's simulator which resulted in bad coverage information being generated.
- Fixed bugs in divide, mod, left shift, right shift and some other expression types
to avoid converting variables that have unknown values to integers (which results
in Covered errors at run-time).
The list of changes is short, but the changes made are very necessary to getting reliable
coverage numbers from Covered. Please get a copy of this version and test it out so that
we can get the stable 0.2 release made ASAP.
* 02/18/2003
Release covered-0.2pre2 made. Bug fixes and enhancements for allowing more Verilog
code to be parsed without spewing parsing errors. The list of open bugs is empty at
the moment. I will be working on enhancing the user documents and development
documents in preparation for the stable release. The stable release will be made
next unless there are new bugs found for which the bug fixes convince me that additional
testing is necessary. The following is a list of the changes for this release.
- Fixed bug with copying instance trees for instances of modules that were previously
parsed and built into the main instance tree.
- Fixing bug in file finder so that only missing modules are displayed after the
parsing phase is completed.
- Updated output of filenames as they are parsed to give more consistent look.
- Fixing bug with leftover tmp* file when missing module error is reported.
- Adding parsing support for pullup, pulldown and gate types though these are not
supported for coverage at the current time (probably will be supported after stable
release).
- Adding parsing support for real numbers in statement delays.
- Fixing case where statement is found to be unsupported in middle of statement tree.
The entire statement tree is removed from consideration for simulation.
- Added preliminary support for parsing attributes though the parsing support is not
complete at this time.
- Fixing bug with line ordering where case statement lines were not being output
to reports.
- Fixing bug with statement deallocation for NULL statements within statement trees.
- Updates to parser for new bison version 1.875
- Added support for named blocks
- Fixing bug with handling of preprocessor directives with leading whitespace.
- Fixes/optimizations to db_add_statement function which avoids stack overflow errors.
- Added check in regard to -i option to score command. Bad -i values would cause no
coverage information to be generated but would not tell user explicitly. Error
message now provided with -i option is not specified but is needed and/or -i option
is incorrect.
- Lots of parser updates to be able to parse UDPs, escaped identifiers, specify blocks,
and some other various Verilog code that was causing parse errors or assertion errors.
- Fixed proper handling of the event type.
- Fixed bug with merging constant/parameter vector values which caused assertion error
in report command when reporting on a merged file.
- Fixed user error message for merge command when CDD files are unable to be read.
- Added new type to CDD for general CDD file information. This allows CDD files from
different testbenches with the same DUT instantiated to be properly merged.
- Fixed problem with generating report from CDD file that has not been scored. Covered
detects that the CDD file has not been scored and outputs an error message to the user
not allowing them to generate these reports.
- Added support for reading bit selects from VCD files (this information was previously
ignored). This was necessary as other simulators bit blast module ports in VCD files.
- Updated look of instance reports to display full hierarchy of an instance instead of
the instance name and the instance name of the parent module. Much easier to locate
the instance in the design now.
- Fixed bug with using -D/-Q option with merge command.
- Added merge regression testing capability to regression suite.
- Updated build environment for RedHat 8.0 requirements.
- Updates to regression suite
- Development documentation updates.
The way that Covered looks and feels for 0.2 stable release is set in stone now. Please
make sure that you test this version as much as possible to get any leftover bugs out of
the code. I only plan on updating documentation, adding code comments, and fixing bugs.
If any bugs are sent in, a 0.2pre3 release will be created, otherwise, I will make
the 0.2 stable release available.
I've got some exciting things in Covered's future in plan after 0.2 stable release,
including FSM support, new text report look, code optimizations, support to be fully
Verilog-2001 compliant, a parallel scoring algorithm, and a new GTK+ interface.
Happy testing!
* 01/05/2003
Happy New Year! Release covered-0.2pre1_20030105 made. This release is primarily a
bug fix release; however, many of the bugs required larger changes than would be
expected before a stable release. The most significant change being to the lexer which
is now split into a preprocessor and a normal lexer (before these two functions were
combined into one). As such, this is the first prelease with a second release most
likely expected before stable release. The following is a list of changes included in
this release.
- Preprocessor split out from lexer to allow proper handling of defined values within
code.
- Added -p option to score command to allow user override of preprocessor intermediate
output file.
- Fixed bug where report output was not squelched when -Q global option specified on
report command line.
- Modified regression suite to verify CDD file generation (was being performed before),
module report generation (new) and instance report generation (new) to make sure that
report output was consistent.
- Fixed bug where integer, time, real, realtime and memory data types used in expressions
where considered to be implicitly defined and given 1-bit values. When these types
are seen in expressions now, they are ignored by Covered (caused nasty segfault).
- Fixed bug when a parameterized module is instantiated more than once in a design
(sent error message to user when this occurred).
- Fixed bug where a parsed module that was required but not at the head of the module
list was not being found by the parser.
- Added internal assertions and code to verify that we never try to overrun arrays
in the VCD parsing/running stage (caused nasty segmentation fault).
- Reorganized code for symtable symbol lookup and value assignment.
- Fixing bug where a parameterized module that was instantiated in a design more than
once was not getting the correct parameter value(s).
- Fixed module search algorithm to reparse a Verilog file that contains a module
that was previously ignored (not needed at the time) but is later found to be
needed.
- Created tree.c and tree.h to handle new module search algorithm and to replace
preprocessor define tree structure.
- Updated development documentation.
- Updates to user manual and manpage for new -p option, notes from this release
and a new section that starts to describe what logic is analyzed by Covered and
which code is not analyzed.
I've got some fairly large designs being run with this version of Covered and the regression
suite has grown to over 130 diagnostics with more on the way. Keep the bug reports coming!
Release notes for the gEDA/gaf 20040111 snapshot
Changes
_________________________________________________________________________________________________________
General / Summary
* Lots of changes in most areas. This release contains the largest amount of changes in quite a while.
Expect bugs, crashes, and general instability. If you tell me about them, I might be able to fix them.
* Probably the biggest set of changes were the addition of multi-line text support. The bulk of the work was
done by Carlos. The text add dialog box and the multi attribute add/change dialog box both support the
adding and editing of multi line text items, however, I am going to change these dialog boxes in a
subsequent release to be a little like the old behavior, but still support multi-line text support. Full
multi-line text support requires that you use gtk+ 2.2.x.
* Also part of the above changes was to get rid of some fixed sized buffers within libgeda and gschem.
Hopefully I have hashed out all the bugs in these changes, but I wouldn't be surprised if I missed
something. Please report all crashes. Thanks.
* Changed the file format a little. Changed the way sch/sym files are versioned and added a field to the
text item to support the multi-line text feature addition. I recommend everybody run gsymupdate and
gschupdate (and verify the resulting files!) to get rid of the log warning message. gEDA/gaf will always
write the new file format for all saved schematic/symbols.
* The v flag (the version of the sym/sch file), in the past, was keyed off of a version date, such as
20030901. Starting with 20040111, I am no longer using this date as the version of the sch/sym file, but
rather I added a new field (number) which is the file format version. The new version line looks like:
v 20040111 1
This is nice that I don't have to update all the symbols, schematics, etc... to get rid of a log warning
message. The current version of the file format is 1. All past files are versioned as 0. As an experiment,
I left all the symbol files at v 20031231 1 and nobody should care/notice. I am planning more changes to
the file format in subsequent releases and this version field will make changing it easier.
* The text object has an additional field which is the number of lines (N) the text item contains. The text
item is then followed by N number of lines of text. Example:
T 48400 59900 9 10 1 0 0 0 3
Line1
Line2
Line3
* The component libraries:
vhdl, verilog, new asic, and the new gnetman
are commented OUT in the system-commonrc file. I did this because there are significant symbol name
clashes between these libraries. If you want to use one of these libraries, please place the appropriate
(component-library "...") string in some rc file. This commenting out is temporary, till I fix the
component name clashing bug (jitterbug#9).
* The component-library-search keyword in the system-commonrc file was commented out. If a directory is
specified for the component-library-search keyword, then libgeda/gschem/gnetlist will automatically find
any directories in the specified directory and add them to the component search path. By having this
keyword in place, this would have undone the above commenting out.
If gschem/gnetlist cannot find your custom component libraries after upgrading to 20040111, then either
comment in the component-library-search keyword back into the system-commonrc file or explicitly add the
custom component libraries to an rc file. The latter action is prefered.
This info was added on 02/08/2004.
* Upgraded all packages to use gettext (GNU gettext) 0.12.1. I don't think that anybody who downloads the
source tarballs will need this particular version, but you will certainly need it if you build the CVS
version.
* Partially applied Carlos' UTF-8 patch for gtk+ 2.2.x. I couldn't test the complete patch, so I will keep
working on this. Moving libgeda to use UTF-8 internally is going to be a bit of work, but the sooner it
happens, the better.
* The gEDA Suite setup program has been improved considerably. It now supports the download of the tarballs
automatically using wget. All you need to get from the gEDA website is the toplevel Makefile and type:
make xinstall and the setup program will do the rest. See below in the build section for more information
on using xinstall. Please report any problems with gEDA Suite setup so it can be further improved.
* Much more documentation that gets installed now (almost all of it). I included Bill Wilson's gsch2pcb
tutorial and Russ Dill's tragesym tutorial. I also am installing all READMEs, so please see the
gedadocs.html file for almost all available documentation on gEDA/gaf. You can access this file via
Help/Manual... in gschem (make sure you have a web browser installed).
libgeda
* Shared library version number now at 20.
* In 20030901, libgeda was accidentally being built without optimization. Fixed in this version.
* Applied Carlos Nieves Onega's multi-line text patch. See below in the gschem for more info. This patch
changed and fixed a lot of things in libgeda, so expect some instability.
* Applied a few more patches by Carlos to perfect the multi-line text support in libgeda (mainly dealing
with support for tabs in multi-line text items).
* Added postscript output for mutli-line text items. This support is really new and not 100% perfect. Expect
some problems here, mainly when you start rotating and changing the alignment of many line text items.
Putting tabs into the text strings is not yet supported.
* Fixed a really nasty bug in o_attrib_get_name_value() which was caused by g_strsplit() not behaving the
same between glib 1.2.x and glib 2.2.x. Be careful when using g_strsplit, especially if you use both
versions of glib. Bug caught by Stuart.
gschem
* Added the --with-stroke command line to specify where ./configure can find the libstroke files.
* Changed the behavior of the print dialog box to close when the user presses the Print button.
* Added the ability to generate PNGs from the command line. Look at gschem/scripts/image.scm for the scheme
script. Command line looks like: gschem -o test.png -s image.scm filename.sch
* Added a schem rc keyword: image-size which lets you set the size of the PNG image generated using the
above guile script.
* Applied Carlos Nieves Onega's multi-line text patch. This patch adds multi-line text support to
gschem/libgeda. This patch made some very deep changes to internals which haven't changed in years, so
expect some instability. Multi-line text is properly supported only when using gtk+ 2.2.x. You will be
able to load schematics and edit multi-line text (in a limited fashion) if you use gtk+ 1.2.x
* Part of the above patch was the removal of a bunch of fixed sized buffers. Hopefully Carlos and I have
fixed all issues surrounding these changes, but expect some instability here as well as we work out the
kinks.
* Applied a patch by Carlos to highlight the proper alignment value in the pull down menu in the Edit
Text... dialog box.
* Fixed the visual alignment of the menu items and hotkeys when using gtk+ 2.2.x.
* Improved the appearance of a few of the dialog box, by mainly adding whitespace. A few dialog box got a
few more touch ups, but nothing too drastic.
* Applied a patch by Carlos to add multi-line attribute editing to the multi attribute dialog box. The
changes for this are not complete and will change in the next release.
* Updated the pt_BR.po with Antonio's UTF-8 version.
* Applied Stuart's multi-select open patch. Now you can select multiple schematics to open using the
File/Open... dialog box. Hold down the shift or control key as you click on filenames.
* Part of Carlos' multi-line text patch was to change the quick rendering of text from a line to a
rectangle. Refined and refactored this code a little to properly display attributes.
* Fixed a long standing bug in the File/Open... and File/Close... mechanisms when dealing with multiple
windows. Bug identified by Karel Kulhav.
* Fixed a long standing bug in the preview window (for schematics and components) where there would be
garbage data in the bottom of the window. The bug only manifested itself under very specific conditions
and only when using gtk+ 1.2.x. I'm quite surprised nobody else complained about it (or rather recently).
* Applied a patch by Carlos to support the new Spanish characters.
* Fixed the invalid scrollbars on startup bug.
* Updated the man page a little bit. Added code to the build mechanism to generate an html version of the
man page, which is installed into the documentation directory.
* Bunch of other improvements and bug fixes.
gnetlist
* Upgraded Bill Wilson's gsch2pcb gnetlist backend to the latest (1.4)
* Applied all of Carlos' DRC2 patches.
* Applied all of Stuart's spice-sdb patches. The included spice-sdb backend should be Stuart's absolute
latest version. A bunch of improvements to various parts of gnetlist were included in these patches.
* Applied of Stuart's patch to the partlist backends.
* Updated the man page a little bit. Added code to the build mechanism to generate an html version of the
man page, which is installed into the documentation directory.
* Added the scheme rc keyword: unnamed-netname which lets you control what the unnamed nets should be
called.
* Add the necessary rules to the Makefiles to install all the backend READMEs into the documentation
directory.
* Applied a patch by Christopher K Eveland to fix a condition where gschem2pcb was picking up a pin when it
should not. If somebody could test gschem2pcb on an existing project and make sure it still works as
expect, it would be greatly appreciated.
* Added the Racal Redac format backend by W. Kazubski.
* Added the new RF Cascade and futurenet2 backends by Dan McMahill.
* Applied a bunch of patches by Dan for doing net aliasing/renaming. These patches touched the C files as
well as various backends.
* Applied a few more patches by Dan to fix some m4 quoting issues with the PCB backends.
* Bunch of other minor bug fixes.
gsymcheck
* No significant changes (lots of pending work though).
* Updated the man page a little bit. Added code to the build mechanism to generate an html version of the
man page, which is installed into the documentation directory.
symbols
* Werner Hoch has fixed a whole slew of symbols in various component libraries. Thanks Werner!
* Added a whole bunch of contributed symbols from various people. Thanks.
* Added a bunch of new Spanish characters by Carlos.
* Removed vhdl, verilog, asic, and gnetman from the system-commonrc file.
geda (gManager)
* Piotr Miarecki added a bunch of features and fixed a few bugs in gManager. Give it a try and let him how
gManager works for you. gManager is looking really nice.
* Integrated Antonio's pt_BR translation. This should work now.
* Added a strategic sleep to the mainloop of gManager to reduce the CPU load.
utils
* Updated Bill Wilson's gsch2pcb to version 1.4
* Add the necessary rules to the Makefiles to install all the backend READMEs into the documentation
directory.
* Integrated Stuart's garchive script.
docs
* Applied a whole bunch of patches from Dan McMahill to the symbol creation guide. These patches added/fixed
information related to the footprint= attribute.
* Started using hyperref.sty for all LaTeX generated documentation, which adds hyperlinks to the pdf files.
* Added a bunch of converted txt -> tex documents. The conversions were done by Dan McMahill.
* Added the Dan McMahill's documentation for the RF Cascade gnetlist backend.
* Rewrote the toplevel gedadocs.html index file to link all the new documentation, readmes, man pages, and
tutorials. The gedadocs.html now file contains almost all existing documentation on gEDA/gaf that I'm
aware of.
* Added a couple of tutorials that people have written. Namely Bill Wilson's gsch2pcb and Russ Dill's
tragesym tutorials. Both of these tutorials are accessible from the gedadocs.html file.
* Explicitly stated in the file formats document that all the file formats associated with gEDA/gaf are
covered by the GPL version 2.0.
* Lots of improvements and fixes to various docs.
examples
* No significant changes.
For more a detailed changes, please look in the appropriate ChangeLogs in the source tarballs.
Changes:
Library Management
* Packages and Device Sets can now be copied into the currently
edited library from other libraries, either through Drag&Drop from
the Control Panel or by using the COPY command's new extended syntax
(see "Help Copy").
* New package variants can now be created by directly using packages
from other libraries, either through Drag&Drop from the Control Panel
or by using the PACKAGE command's new extended syntax.
* The packages of the currently edited library can now be updated with
those from other libraries, either through Drag&Drop from the Control
Panel or by using the UPDATE command's new extended syntax.
And more! please review this link to see a full list of changes:
http://www.cadsoft.de/version41.htm
A partial list of what's new is:
- Internal resolution changed to 0.01 mil from 1.0 mil
- Improved DRC checking
- Mirroring/rotating of buffers
- Undo works on trace optimizations
- Fixed polygon undo bugs
- Fix arc DRC bugs
- Added local measurement for line drawing
- Added mode for polygon viewing to help examing planes
- Added new footprint libraries (amp, amphenol, bourns, johnstech,
minicircuits, panasonic)
- Added new footprints to the geda library
- Other bug fixes
Gnucap 0.34 release notes (02/01/2004)
This is a bug fix and compatibility release.
1. Fix bug causing incorrect interpolation of backwards tables.
2. Fix tanh overflow bug.
3. Fix some parsing bugs.
4. Fix occasional "double load" bug.
5. Fix AC sweep with one point.
6. Transient start time really works.
7. Fix occasional assert fail after option short is changed.
8. Fix memory leak resulting from failure to delete unused common.
9. Fix a Z probe bug that sometimes gave wrong answers.
10. Fix a limiting bug that sometimes caused non-convergence.
11. Configure handles isnan.
12. Improvements to logic initialization. It is still not correct.
Some things that are still partially implemented:
1. BSIM models, charge effects, "alpha0" parameter. (computed then
ignored)
2. Configure still doesn't handle everything.
3. The model compiler still requires too much raw coding.
4. Named nodes. If you set the option "namednodes", it will support
named nodes, but some things don't work, so it is off by default.
5. The preliminary IBIS code is now included. For now, it is a
standalone executable, that reads an IBIS file and generates a
netlist. The netlist requires some editing to use, and is not fully
compatible anyway. It is included in hopes of recruiting help in
finishing the project.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. An occasional bogus calculation in MOSFETS occurs when a device is
reversed. This sometimes causes nonconvergence.
3. Initialization is strange when repeating an analysis without an
intermediate edit.
Hot items for a future release (no promises, but highly probable):
1. Verilog-AMS and VHDL-AMS support.
From the NEWS file:
This release is basically a 0.2.1 release with the available bug fixes
patches applied to it. This should make getting a stable release less
tedious.
rather than using LOWER_OPSYS. This is because the couple of os's
that had correct targets were the same and others that pkgsrc works on
aren't listed at all (like solaris). Fixes build problems noted on
solaris.
-- Release 0.15 --
2003-10-06 Stefan Petersen <spe@stacken.kth.se>
* src/draw_amacro.c: Drawing of aperture macro primitive 7 was
severly broken. Revealed by Drew Moore who sent an example
along. Thanks Drew! Closes bug #818307.
2003-09-28 Stefan Petersen <spe@stacken.kth.se>
* src/gerber.c: Patch from Peter Brueckner. Some Gerbers don't
have G04 but just G4. Peters patch fixes that for G- and M-codes.
2003-09-08 Stefan Petersen <spe@stacken.kth.se>
* src/gerber.c: Patch from Simon Munton to fix a problem with polygons
sometimes not being filled properly. Closes bug #800928 (which
he promptly had submitted).
* src/gerber.c: Another patch from Simon. This time it fixes
circular polygon outlines by with a number of short segments.
Closes bug #603183, which was almost a year old. Thanks Simon!
curses.buildlink2.mk. This was wrong because we _really_ do want to
express that we want _n_curses when we include the buildlink2.mk file.
We should have a better way to say that the NetBSD curses doesn't
quite work well enough. In fact, it's far better to depend on ncurses
by default, and exceptionally note when it's okay to use NetBSD curses
for specific packages. We will look into this again in the future.
Inspired by FreeBSD "ports".
Fix the PLISTs accordingly.
Also, while at it, remove now obsolete compileall.py calls in post-install
targets and insure that extension.mk is in included before builinlinks of
other Python modules.
Discussed with/ok'ed by drochner@.
This update is a collection of little improvements and a significant
verhaul of hardcopy plot and export.
Hardcopy and documentation output can now be obtained using either graph
or Gnuplot. A dialog box allows choosing output formas and a few other
settings. Additional plot/export filters can be plugged in by writing a
suitable scheme module.
There's a data-export function for extracting and saving a subset of a
datafile as ascii.
The stacking/drawing order of waveforms can be changed.
Selected waveforms are now drawn in a highlighted style.
