Commit graph

13 commits

Author SHA1 Message Date
tv
f816d81489 Remove USE_BUILDLINK3 and NO_BUILDLINK; these are no longer used. 2005-04-11 21:44:48 +00:00
jmmv
c434a48a28 Add a missing dirrm line. Closes PR pkg/29649 by Cesar Catrian C. 2005-03-20 18:21:39 +00:00
agc
7ea6ce3da9 Add RMD160 digests in addition to SHA1 ones. 2005-02-23 14:59:23 +00:00
dmcmahill
71e41985f5 update to electric-7.00
This is a major version bump and represents many many bug fixes and
lots of improvements.  The scope is fairly broad and can't really
be summarized.  See the ChangeLog in the distfile for a complete
list of changes.
2004-12-01 04:47:53 +00:00
tv
c487cb967a Libtool fix for PR pkg/26633, and other issues. Update libtool to 1.5.10
in the process.  (More information on tech-pkg.)

Bump PKGREVISION and BUILDLINK_DEPENDS of all packages using libtool and
installing .la files.

Bump PKGREVISION (only) of all packages depending directly on the above
via a buildlink3 include.
2004-10-03 00:12:51 +00:00
snj
7066c62ce6 Convert to buildlink3. 2004-04-11 19:08:15 +00:00
xtraeme
66db214aec There's no need to use 'USE_X11BASE' in electric package, we'll use
USE_X11 instead, bump PKGREVISION.
2004-01-28 12:33:58 +00:00
grant
91f00f1cbc s/netbsd.org/NetBSD.org/ 2003-07-17 21:21:03 +00:00
jmmv
f1446ddf2b Drop trailing whitespace. Ok'ed by wiz. 2003-05-06 17:40:18 +00:00
wiz
246e1b5e85 s/${ENV}/${SETENV}/, noted by Kevin P. Neal in connection with PR 19586. 2003-02-09 14:38:51 +00:00
jlam
926a56fbd5 buildlink1 -> buildlink2 2002-09-21 06:05:55 +00:00
jlam
ec8f6ad65a Note explicitly that this package is USE_X11BASE. Currently, it relies on
motif.buildlink.mk to define it.
2002-04-23 02:08:51 +00:00
dmcmahill
231ebb4c4f Import electric-6.05
-----

Electric is a sophisticated electrical CAD system that can handle
many forms of circuit design, including:
     Custom IC layout (ASICs), Schematic drawing, Hardware description
     language specifications, Electro-mechanical hybrid layout

Electric has these CAD operations:
     Design rule checking (3 options), Electrical rule checking,
     Simulation and simulation interface (12 options), Generation (3 options),
     Compaction, Compensation, Routing (4 options), VHDL compilation,
     Silicon compilation, Network consistency checking (LVS),
     Logical Effort analysis, Project Management

Electric handles these types of design:
     MOS (6 CMOS variations, 1 nMOS variation), Bipolar and BiCMOS,
     Schematics and printed circuits, Digital filters, Temporal logic, Artwork

Electric handles these file formats:
     CIF I/O, GDS I/O, EDIF I/O, DXF I/O, SDF Input,
     SUE Input, VHDL I/O, Verilog Output, EAGLE, PADS, and ECAD Output,
     PostScript, HPGL, and QuickDraw output
2002-03-13 01:39:18 +00:00