It has been a long time since the last update to this snapshot package.
Besides the various upstream changes, also
- add LICENSE
- add DESTDIR support (partially enabled by upstream fixes)
Release Notes for Snapshot 20090923
This is the first snapshot after the split from the 0.9
release. Mostly, this snapshot is loaded with 7 months worth of bug
fixes.
This changes the buildlink3.mk files to use an include guard for the
recursive include. The use of BUILDLINK_DEPTH, BUILDLINK_DEPENDS,
BUILDLINK_PACKAGES and BUILDLINK_ORDER is handled by a single new
variable BUILDLINK_TREE. Each buildlink3.mk file adds a pair of
enter/exit marker, which can be used to reconstruct the tree and
to determine first level includes. Avoiding := for large variables
(BUILDLINK_ORDER) speeds up parse time as += has linear complexity.
The include guard reduces system time by avoiding reading files over and
over again. For complex packages this reduces both %user and %sys time to
half of the former time.
Release Notes for Icarus Verilog Snapshot 20070227
* Fix some problems with specify block parsing. Detect some cases that
are parsed but not properly implemented yet and issue warnings or
errors. Also fixed a few problems with inertial delay model timing.
* Detect is some cases Verilog source errors that can be better
reported to users. This includes more specific error messages for
certain syntax errors.
* Fix problems with overridden continuous assignments.
* Hide bool types from logic type as far as VPI is concerned, for the
sake of compatibility.
* Fix a variety of code generator expression lifetime bugs that caused
obscure (and wrong) output results in behavioral code.
* iverilog-vpi uses the compiler selected at build time.
* Rework handling of strings to handle escape sequences properly.
* Fix some handling of real values in some expression types.
* Get padding of sized, unsigned numbers when x or z are involved.
* Many, many more misc. bug fixes.
* Add an assert mechinism that improves usefulness of bug reports by
reporting source file line numbers when available.
* Compile fixes, using inttypes.h instead of stdint for portability.
* Various spelling fixes.
Release Note for Icarus Verilog Snapshot 20070123
Handling of arrays has been rewritten to allow support for net
arrays. This caused ivl_target API changes, as well as elaboration and
vvp run time changes. There may be bits of the old method lingering in
the source code.
Improve support for constant power (**) expressions, and other
constant exppressions that are passed to functions/tasks.
Improve elaboration of for-loop increment expressions. There were some
bugs there that are not fixed.
Fix argument width calculations for shift operations.
Constant ector expressions can have real constants. Handle this at run
time where needed.
Fix some bad lookaside optimizations for assignments to l-value part
selects.
* Release Notes for Icarus Verilog Snapshot 20061009
The Big news is support for delay path timing is specify blocks. This
includes delay paths and specparams. Back annotation of specify path
timings are not yet implemented.
The "-g" flag has been made a bit more general so that individual
compiler features can be turned on/off. This for example allows for
turning off specify block support and Icarus Verilog extensions, as
well as select language generation.
A variety of bug fixes have been included.
- Missing symbols on Windows fixed.
- mingw build instructions reworked.
- Fix internal handling of -D__ICARUS__ define
- Fix crash of driver when -M flag is used.
- Fix configure detection of host in some subdirectories.
- Handle non-constant delays of index non-blocking assignments.
- $scanf support for real values.
- Fix scheduling of RWsync vs. ROSync callbacks.
- Fix vpi_put_userdata return value.
The iverilog-vpi command now allows .cpp files to stand for C++
source.
last packaged snapshot. Those are:
--------------------------------------------------
Release Notes for Icarus Verilog Snapshot 20060215
--------------------------------------------------
* Part select of memory words should now work according to
Verilog-2001. This also led to some cleanup of the handling of types
internally, as well as some infrastructure for general arrays.
* Minor fix to parsing of (* *) attributes.
* Fix rounding of reals to integers.
* Clean up some of the vvp engine related to memories. Remove some
dead instructions.
--------------------------------------------------
Release Notes for Icarus Verilog Snapshot 20060409
--------------------------------------------------
the most substantial difference in this snapshot the first signs of
generate support. The compiler now supports generate loops and has
been tested with examples that include wires and gates within the
generate scheme. The regression test suite has very few generate
tests, so any concise self-testing test programs that use generate
would be helpful.
Also, instance arrays that use overridden parameters now work
properly.
Task arguments are a bit more flexible in order to support vendor
(notably Xilinx) models that use more interesting task arguments.
Runtime support for bi-directional ports had some bugs fixed, along
with some other minor run-time bugs. Also, the runtime gains support
for typed parameters. And also, there are some new runtime callbacks
for events and memories.
Parameters had a few types related bugs fixed. They are a bit more
flexible now.
And various minor compilation errors have been fixed. This includes
C/C++ compilation errors fixes, and some configure/Makefile tweaks.
--------------------------------------------------
Release Notes for Icarus Verilog Snapshot 20060618
--------------------------------------------------
Add support for system functions in continuous assignments.
Allow concatenations as arguments to inout ports. This comes with a
small variety of internal part select and concatenation bug fixes.
Fix some bugs in constant propagation through ternary expressions.
Fix broken subtraction if small constants in certain cases.
Fix a few datatype mismatch errors.
Make $readmem give warning when input is inadequate for requested
range.
Fix runtime of nand in continuous assignments.
Fix synchronous user defined primiteves to only follow edges.
Fix a runtime error in some thread delays processing.
Improve limited genvar expression handling.
Start a rework of expression elaboration. Make elaboration aware of
the expression context width when appropriate in order to better
handle expression width and padding.
Fix the make rules for parse.cc to reflect that they come from the
same source. Fix the autoconf.sh to configure the stub target.
Fix portability of the lexor source files on Windows systems. Get rid
of the isatty references.
Make a stub lround when the system version is missing.
--------------------------------------------------
* Release Notes for Snapshot 20060809
--------------------------------------------------
Some handling of real values is improved. Real valued literals are
handled in net contexts (continuous assignment, etc.). Also, modulus
of real operands now works. (This is an extension to the Verilog
standard.)
The power operator (**) now works.
Signed right shift works properly now.
The $sscanf and $fscanf are introduced, and work at least for basic
numeric values.
The release function now works to undo general force statements, and
not just contant force statements.
Delay constants up to 64 bits are supported. This at first doesn't
seem like an issue, but when precisions are mixed, it becomes
surprisingly easy to overflow 32bit delays.
The driver is reworked to pass many preprocessor details through a
temporary file instead of on the command line of a system(3)
call. This prevents confusing and incorrect shell processing of
complex strings passed as values to -D flags.
Various other little fixes.
and add a new helper target and script, "show-buildlink3", that outputs
a listing of the buildlink3.mk files included as well as the depth at
which they are included.
For example, "make show-buildlink3" in fonts/Xft2 displays:
zlib
fontconfig
iconv
zlib
freetype2
expat
freetype2
Xrender
renderproto
RECOMMENDED is removed. It becomes ABI_DEPENDS.
BUILDLINK_RECOMMENDED.foo becomes BUILDLINK_ABI_DEPENDS.foo.
BUILDLINK_DEPENDS.foo becomes BUILDLINK_API_DEPENDS.foo.
BUILDLINK_DEPENDS does not change.
IGNORE_RECOMMENDED (which defaulted to "no") becomes USE_ABI_DEPENDS
which defaults to "yes".
Added to obsolete.mk checking for IGNORE_RECOMMENDED.
I did not manually go through and fix any aesthetic tab/spacing issues.
I have tested the above patch on DragonFly building and packaging
subversion and pkglint and their many dependencies.
I have also tested USE_ABI_DEPENDS=no on my NetBSD workstation (where I
have used IGNORE_RECOMMENDED for a long time). I have been an active user
of IGNORE_RECOMMENDED since it was available.
As suggested, I removed the documentation sentences suggesting bumping for
"security" issues.
As discussed on tech-pkg.
I will commit to revbump, pkglint, pkg_install, createbuildlink separately.
Note that if you use wip, it will fail! I will commit to pkgsrc-wip
later (within day).
A few new features have been added to allow proper simulation with
newer Xilinx UNISIM models. (They are starting to use Verilog 2001
features.) And also various bug fixes in this release.
-- Primitive and continuous assign delays can now be non-constant. This
needed some new run-time support, so vvp had a slight format change,
and certain new optimizations follow as a result.
-- Bug handling certain constant sub-expressions in concatenation
expressions. Also, allow concat expressions in constant contexts.
-- Support for wide divide expressions.
-- Fixes for stubborn compilers.
-- Fix bugs in padding of signed expressions.
-- More fixes for following the data types of expressions.
Release Notes for Icarus Verilog Snapshot 20041004
Some minor Makefile bugs have been fixed, and source file text
formatting has in some cases been normalized for release. Also,
configure scripts have been factored for a more consistent build.
Fixed continuous assignments to carry strength when needed for correct
behavior. This bug led to subtly incorrect reset behavior, but could
have caused strength modeling errors in a variety of situations.
Fixed some <= vs >= behaviors to be consistent. The results of these
comparisons, when sized values are involved, are more standard now.
in the process. (More information on tech-pkg.)
Bump PKGREVISION and BUILDLINK_DEPENDS of all packages using libtool and
installing .la files.
Bump PKGREVISION (only) of all packages depending directly on the above
via a buildlink3 include.
The big news is that module instance arrays now work. Gate and UDP
instance arrays have worked for a while, but module instance arrays
were more tricky because of the scope arrys they create. The issues
have been dealt with, and module instance arrays are now supported.
An interesting but subtle set of bugs in the evaluation of ternary
expressions has been fixed. The problems expressed themselves when the
condition expression was constant.
Degenerate wait statements now work properly.
The @* syntax apparently missed sensitivities in l-value expressions
of assignment statements. This led to subtle bugs in carefully crafted
bits of code.
Verilog attributes are properly parsed in a few more contexts. Also,
some specify syntax cases have been fixed.
Some minor spelling and documentation errors have been fixed, along
with assorted compiler warnings.
changes include:
Added support for the `default_nettype directine, including the
default net type of "none", which turns off implicit net declarations.
Signed /, % and >>> in nets should now work properly. Also, various
operators of all sorts applied to constants have been improved.
Ranges now work on localparams.
Added the system tasks $unsigned, $is_signed, $mti_random and
$mti-dist_uniform. See the make README.txt for a description of these
system functions. Also, flesh out the standard random number
generators to match the sequences generated by other compilers.
There is now an "sft" file that describes to the compiler the return
value of system functions. This allows user supplied system functions
to have interesting return types. See "SYSTEM FUNCTIO TABLE FILES" in
the iverilog man page. Include a sft file for the system functions,
and move the system functions over to that mechinism.
Fix the behavior of $fgets in tight fitting result buffers.
A variety of compilation environment fixes have been added. These
involve configure scripts and Makefiles.
And of course a variety of other bug fixes, and so on and so forth.
* Release Notes for Icarus Verilog Snapshot 20040606
Ports of primitives can bind by name as well as by position. Also
support Verilog 2001 style port declarations for primitives.
System function return types can now be specified by system function
table files. System Function Table Files are described in the iverilog
man page. Also include better system function return types in VPI.
Non-blocking assign of real values to real variables now works.
Properly handle nul strings ("") as 8bit values. This is a weirdness
legacy of XL.
Fix some synthesis problems for logical OR and logical AND. Bitwise OR
and AND were fine. These fixes affected simulation as well.
Handle wait statements with all sorts of constant values. These are
sometimes weird, bug legal.
Handle Negative value reals, and a few other bugs related to real
numbers.
Change internal use of identifiers to perm_strings for better
performance.
Functions returning unsupported types now generate error
messages. Previously, they would quietly generate bad
code. Infrastructure is also added to eventually support arbitrary
function return types.
Better compile-time support for Cygwin vs mingw32.
The ipal target is removed from this source. (ipal is now an add-on
package that is compiled seperately.)
There was a couple of snapshots since february; besides bugfixes the
major highligths might be:
-handling of real values at various places
-support for library modules (esp cadence PLI1)
-better FPGA support (esp Virtex II)
-"vvp" interactive mode added
Also converted to buildlink2, and dependencies to libz, libbz2 and
readline added.
This is the first packaged (in pkgsrc) snapshot after the verilog-0.7
release.
This snapshot adds preliminary support for real variables to the language
to the features already found in verilog-0.7.
Release Notes for Icarus Verilog Snapshot 20021019
The synthesizer now detects asynchronous set/reset inputs to DFF
devices. The fpga and vvp code generators have been updated to support
these signals.
The vvp code generator also gained some register management code that
improves the thread register usage. This redoces code size for certain
common cases, and thus improves simulation performance.
The requirements on `ifdef and related compiler directives has been
relaxed, to correspond to more common behavior.
The parameter range support crashed if the range expressions had
parameters in them. This is fixed, and some signed-ness bugs fixed
along with it.
Rearrange some of the configure script tests to assure better
compatibility accross platforms.
Release Notes for Snapshot 20020828
This snapshot adds support for parameter and localparam bit
ranges. This is a IEEE1364-2001 feature, although some -1995 compilers
have supported it in the past.
Fixed a *nasty* and slippery bug with the evaluation of bit select of
nets. (Bit select of variables was unaffected.) The symptoms did not
clearly point to the problem, so bugs related to it were often mis-
reported.
Gate delays were lost when constants were propagated to their
inputs. This is fixed for the known broken cases. Also, mux output
delays have been fixed. Also, release statements that apply to elided
nets are turned into no-ops.
The r-values of non-blocking assignments are now precalculated at
compile time, if possible, as is done with blocking assignments. This
speeds up constant propagation, and is more thorough.
Also optimize subtraction of small constants from vectors, with the
new %subi instruction in vvp. This saves some in code size and thread
footprint.
Handling of x in r-value bit selects and memory word selects did the
wrong thing. Now they do the right thing. Also, x in the selector of
?: ternary operators does the right (and complicated) thing now. In
the process, a fork-join code generator bug was fixed.
Several bugs with time formatting have been fixed.
Temporaries in sequential blocks are detected by the synthesizer, and
converted into wires when needed. This expands support for
combinational logic synthesis.
many improvements and bug fixes since the last packaged snapshot including:
-added the $sizeof system function as a builtin
-In VPI, the simulator event callbacks now work
-Concatenation expressions in parameters were broken are broken
-added the vpiModule iterator to VPI scope handles
