Gnucap 0.33 release notes (01/12/2003)
This is a bug fix and compatibility release.
0.32 was not widely distributed due to password problems and a heavy
work load, so the release notes are repeated after the current ones.
New features:
1. Add inductance probes, like capacitor.
Bug fixes:
1. Fix xprobe duplicate default arg bug - shows in g++3.2.
2. Fix bug that sometimes caused a crash when changing a model after
analysis.
3. Fix bug that caused an assert to fail (debug build) after removing
a probe from an element.
4. Fix a dumb typo hack bug ddHAS_READLINE. Now history and command
line editing really works. It was working, but somehow the hack
slipped into the release code.
=================================================================
Gnucap 0.32 release notes (09/30/2002)
New features:
1. Series resistance in the diode. It took 5 minutes to do,
so it is embarrasing that it wasn't done before.
2. History and command line editing, using Gnu Readline. Thanks to
Simon Hoffe for sending me the patch.
3. More parameters in the BJT model. This gives it better
compatibility with commercial simulators. These parameters are beyond
Spice 3f5.
4. "M" parameter in diode, BJT and MOS devices. M is the number of
parallel devices. Some commercial simulators have this.
Changes that may or may not be improvements.
1. The definition of the transient option "UIC" has changed. It is
now Spice compatible, which means to not attempt to do any solution or
consistency check. Just apply the values, assuming anything that
isn't specified is 0. The old behavior was to attempt a solution
while holding the IC values.
Bug fixes:
1. voltage sync bug. It still doesn't fix the MOS 2 convergence
problem.
2. Fix memory leak in POLY components.
3. Fix bug in Fourier that sometimes causes overrun (crash) and time
sync errors.
4. Modelgen: fix bug in list parsing.
5. Some changes to eliminate warnings when compiling with g++ 3.1.
6. Use Euler differentiation on first step, because trap used a value
that cannot be known then. Usually, this doesn't make much
difference, but there are a few cases where the error can get
magnified and trigger trapezoidal ringing, leading to a totally bogus
result. It most cases, you could hide it with small enough steps.
These cases should work with default settings now.
7. Fix bug that sometimes caused incorrect handling of initial
conditions (UIC),
8. Fix bug that caused continuing a transient analysis to give
incorrect results.
Significant internal changes:
1. The inductor uses all of the same support functions as the
capacitor, including "integrate", which is now correctly called
"differentiate".
2. Most of the code is in place for named nodes. It mostly works and
can be turned on with the option "namednodes". It is off by default
because it is not complete. Most likely, it will be finished in the
next release.
Some things that are still partially implemented:
1. BSIM models, charge effects, "alpha0" parameter. (computed then
ignored)
2. Configure still doesn't handle everything.
3. The model compiler still requires too much raw coding.
4. Named nodes. If you set the option "namednodes", it will support
named nodes, but some things don't work, so it is off by default.
5. The preliminary IBIS code is now included. For now, it is a
standalone executable, that reads an IBIS file and generates a
netlist. The netlist requires some editing to use, and is not fully
compatible anyway. It is included in hopes of recruiting help in
finishing the project.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. An occasional bogus calculation in MOSFETS occurs when a device is
reversed. This sometimes causes nonconvergence.
3. The "modify" command with multiple arguments seems to take only the
first one. It used to work, but is broken in this release. I am not
sure when it broke.
From the NEWS file:
* Changes in Dinotrace 9.1i 03/07/2003
*** Display values with appropriate leading 0s. [Dan McMahill]
*** Fix 0 extension of verilog values. [Dominik Strasser, Bill Welch]
Transcalc is an analysis and synthesis tool for calculating the
electrical and physical properties of different kinds of RF and
microwave transmission lines.
Transcalc was somewhat inspired by the functionality of Agilent
Technologies' commercial program linecalc. Transcalc aspires to be
more functional in the long run and well-documented with appropriate
references to formulas that are used. Transcalc is built using the
GIMP toolkit (GTK) for its GUI interface.
For each type of transmission line, using dialog boxes, you can enter
values for the various parameters, and either calculate its electrical
properties (analyze), or use the given electrical requirements to
sythesize physical parameters of the required transmission line.
Available transmission lines (this list will expand with subsequent
releases):
* microstrip
* rectangular waveguide
* coax
* coupled microstrip
* You cannot compile with backend anymore, switch is removed. In last
release this caused compilation error due to bit rot.
* Drawing of arcs is a constant headache. Mark Whitis found another
case that I had missed out. Clockwise arcs all of a sudden started
to be drawn as counter-clockwise.
* Arcs with very small angle differences could either be a complete
circle or a very small part of an arc. Calculating the angles with
integers wasn't sufficient, anyhow. They are now doubles all the way.
* Aperture macro primitive 1 was a _filled_ circle.
* Image rotate used to cause warnings that it wasn't implemented. Now
if the file has an image rotate on zero degrees there is no warning
(yes I've seen it).
* Dan McMahill discovered that if you tried to swap with an unused layer
gerbv segfaulted.
* Peter Monta submitted patch for incremental coordinates.
* No traces of Guile left...
Makefiles simply need to use this value often, for better or for
worse.
(2) Create a new variable FIX_RPATH that lists variables that should
be cleansed of -R or -rpath values if ${_USE_RPATH} is "no". By
default, FIX_RPATH contains LIBS, X11_LDFLAGS, and LDFLAGS, and
additional variables may be appended from package Makefiles.
Quick summary of changes:
- works with guile-1.6.3 now
- Norwegian/Danish/German character fixes
- PNG output now has some of the objects appearing to have the right thickness.
- added Russian translation
- bug fix in postscript output
- non-applicable menu choices are now greyed out
- fixed PADS netlist output bug
- added several components to library
- added multisheet refdes renumber utility
- several other bug fixes.
The previous version was extremely out of date and the distfile is no
longer available.
Many, many changes since the last packaged version. New 'tuner' feature
added. New models added. Several bug fixes too numerous to list.
in recent bulk builds.
Release covered-20021214 made. This release is a bug fix release. See list below
for details. Bugs that lead to infinite looping in the score command and segmentation
faults should now be cleared up. Please let me know if there are any other bugs that
need to be addressed before first stable release. Development documentation updated
to match changes in files. Regression suite has been updated quite a bit from last
time. There are now over 125 diagnostics in the regression suite (my goal was to
write about 100 before first stable release).
- Segmentation fault fixes in report command
- Parser can now handle all net types (not just wire). Diagnostics added to regression
suite to verify their proper handling.
- Parser updated to handle net declaration assignments (e.g., wire a = b & c;).
Diagnostics added to verify proper handling.
- Added human-understandable error messages in parser to help identify file and
line number along with a quasi-helpful error message description.
- When parser error is found, Covered exits after parsing phase without continuing
to write CDD file.
- Fixed bug where a multi-bit select expression existed in a module that was
instantiated more than once. Assertion error fired in this case.
- Updated regression suite for VCS testing.
- Fixed bug where parameters were used in modules that were instantiated more than
once.
- Fixed bug that dealt with parameters (see param6.1.v for test case).
- Fixed bug where a delay statement was the last statement in a statement block used
by Covered. Added diagnostics to verify correct behavior.
- Fixed infinite loop problem with db_add_statement function.
- Fixed infinite loop problem with statement_set_stop function.
- Fixed bug with parsing order. When an instance is found for a module that has
already been parsed, the instance was incorrectly being handled. Bug replicated
with instance6.v diagnostic.
- Fixed output of edge-triggered events to add @(...) around the expression (they
were easily confused with other code that could exist on the same line).
- Fixed bug in parser to not allow module to be parsed more than once.
- Fixed bug that lead to an assertion error (see instance6.1.v for test case).
- Fixing bug with calculating list and concatenation lengths when MBIT_SEL
expressions were included.
- Changed Covered's handling of -y directories. Before, all files in these directories
were fed into the parser to look for missing modules. Now, when a module is needed,
the module name is used to find the matching filename in the -y list (basically,
the -y option works like the -y option in Icarus Verilog and VCS). This fix really
streamlined the parsing phase and fixed several bugs.
- Memory declarations are now properly ignored (produced segmentation fault previously).
- Fixed report command to display all lines and expressions in order according to
their line number (the problem is REALLY fixed now).
- Removed hierarchical references from being scored.
All in all, you should notice a huge improvement in the parsing speed, syntax errors are
reported better, more Verilog syntax should be handled properly, the score command will
run a bit faster than before, and the reports should be a bit easier to read. Segmentation
faults and assertion errors should become lesser in number (if not gone altogether?).
I am feeling pretty confident that we are getting close to a stable release as I have
been able to generate a CDD file for a chip that is millions of gates in size (CDD file
was created in the range of 30 - 45 seconds!) Keep the bug reports coming. I have some
things to work on for next release already.
This is the first packaged (in pkgsrc) snapshot after the verilog-0.7
release.
This snapshot adds preliminary support for real variables to the language
to the features already found in verilog-0.7.
Many improvements such as support for mixed dielectric systems and several
bitmap generators for common structures to allow quick application of the
tool. Several bug fixes as well. Voltages outside a shield are set to zero
which fixes a reported result in older versions. Many other improvemnts
and bug fixes are listed in the ChangeLog in the distfile.
have it be automatically included by bsd.pkg.mk if USE_PKGINSTALL is set
to "YES". This enforces the requirement that bsd.pkg.install.mk be
included at the end of a package Makefile. Idea suggested by Julio M.
Merino Vidal <jmmv at menta.net>.
This release represents many bug fixes, expanded language coverage,
greatly enhanced xilinx fpga synthesis and several performance enhancements.
The complete list is rather long.
GDSreader - simple Calma (GDSii) parser/printer tool.
This software has as target the printing/plotting/displaying of Calma (GDSii)
files without using true layout editors. I had once to visualize an unknown
Calma file and customizing LEdit or Magic (the two layout editors I had access
to) was so difficult that I decided to write this program.
Current status:
- gdsreader is in an alpha stage and you should not expect too much from it;
- the Calma files are almost completely parsed (had no layout example that
makes use of BOX/NODE elements);
- given a Calma structure name, a PostScript file and a HPGL/2 file are
generated. The way each layer is handled is controlled by an ASCII
configuration file. The properties that can be set are color, fill (only
solid is supported), hatch (simple or cross, the angle and spacing are user
customizable too).
In order to produce an useful PostScript output, you need to write a
configuration file (default is .layers.config). The one you'll find with the
distribution is suitable for the Calma example test.gds (an actual Bandgap
reference).
This represents many many improvements and bug fixes. A few items to
note are that the attributes used by the symbol library have been
greately cleaned up and unified. You may want to run gsymupdate and gschemupdate
if migrating from older versions of the tools.
This is a development snapshot. Packages of the released/stable
versions will be imported as 'cad/covered' when available.
Covered is a Verilog code coverage analysis tool that can be useful
for determining how well a diagnostic test suite is covering the
design under test. Typically in the design verification work flow, a
design verification engineer will develop a self-checking test suite
to verify design elements/functions specified by a design's
specification document. When the test suite contains all of the tests
required by the design specification, the test writer may be asking
him/herself, "How much logic in the design is actually being
exercised?", "Does my test suite cover all of the logic under test?",
and "Am I done writing tests for the logic?". When the design
verification gets to this point, it is often useful to get some
metrics for determining logic coverage. This is where a code coverage
utility, such as Covered, is very useful.
Please note that this package is a development snapshot and while it
contains the latest and greatest features, it may be buggy as well.
There is a seperate package which is made of the stable releases.
Changes since last version:
* fixed bug which caused huge memory usage and crashing when zooming way
in to a layout
* Two bugs in aperture macros fixed; one caused "multi macro" macros not
to work properly and the other was related to primitive 20.
* The Debian build system discovered that I checked if unsigned were -1.
* Some cleanup/speedup when parsing Gerber by removing nested strncmp's
with a switch/case.
* RS274D caused segfault.
* If %SR%, %SF% and %AS% are defined to their default values the compiler
doesn't complain anymore. I still don't handle them if they are non
default values.
* In some strange corner case we managed to sometimes get spurious lines
showing up on the image.
* Strange drill files from Orcad386 handled better (we all know what Pitch
thinks about Orcad:-) ).
* Dino Ghilardi has contributed some code to be able to set the scale
explicitly. That can be used when printing PNG's generated by gerbv.
He has also written a text on how to actually get them out on the printer.
It is in doc/PNG-print/PNGPrintMiniHowto.txt.
* Round off when converting from inches to pixels changed so poured areas
built up by several lines now seems to fill. Before the change you could,
at certain zoom levels, see gaps that wasn't there.
jmmv at menta dot net.
TkGate is a digital circuit editor and simulator with a Tcl/Tk based
interface. TkGate includes a large number of built-in devices
including basic gates, memories, ttys and modules for hierarchical
design. The simulator can be controlled either interactively or
through a simulation script. Memory contents can be loaded from
files, and a microcode/macrocode compiler (gmac) is included to create
tkgate memory files from a high-level description. The simulator
supports continous simulation, single step simulation (by clock or
epoch) and breakpoints. Save files are in a Verilog-like format.
TkGate also includes a number of tutorial and example circuits which
can be loaded through the "Help" menu. The examples range from a
simple gate-level 3-bit adder to a 16-bit CPU programmed to play the
"Animals" game.
TkGate has a multi-langauge interface with support for English,
Japanese, French and Spanish.
Release Notes for Icarus Verilog Snapshot 20021019
The synthesizer now detects asynchronous set/reset inputs to DFF
devices. The fpga and vvp code generators have been updated to support
these signals.
The vvp code generator also gained some register management code that
improves the thread register usage. This redoces code size for certain
common cases, and thus improves simulation performance.
The requirements on `ifdef and related compiler directives has been
relaxed, to correspond to more common behavior.
The parameter range support crashed if the range expressions had
parameters in them. This is fixed, and some signed-ness bugs fixed
along with it.
Rearrange some of the configure script tests to assure better
compatibility accross platforms.
Yet another bunch of bugs in different corner cases of Gerber files
has been fixed. Many fixes in polygon area fill, some fixes in calculating
circles, a statically allocated array caused strange stray segfaults when
drawing aperture macros.
A bunch of new command line switches. Most important are:
* --display: use as in all other X-programs, ie open window from a remote
computer.
* --geometry: Sets the geometry. Usually gerbv guess the resolution of
your window and sets the window size accordingly. If you for instance
have a bigger virtual window than actual screen the window can get quite
big. With this switch you can override with for example --geometry=400x300
Fixes in drill file parser. Many drill files don't have drill sizes in them,
else perfectly valid files. Pitch fix makes gerbv parse drill files even
though they don't have drill sizes defined, but under protest.
Greatest fix of them all. Super imposing. Handles paint-scratch-paint
more proper. Changed dramatically how different layers are drawn "on
top of each other".
Changes in Dinotrace 9.1h 08/30/2002
*** Save_duplicates is now on by default.
**** Fixed several bugs when save_duplicates is enabled.
**** Updated Windows install. [Greg Loxtercamp]
**** Fixed coredump reading wide ascii traces. [Vitaly Oratovsky]
Release Notes for Snapshot 20020828
This snapshot adds support for parameter and localparam bit
ranges. This is a IEEE1364-2001 feature, although some -1995 compilers
have supported it in the past.
Fixed a *nasty* and slippery bug with the evaluation of bit select of
nets. (Bit select of variables was unaffected.) The symptoms did not
clearly point to the problem, so bugs related to it were often mis-
reported.
Gate delays were lost when constants were propagated to their
inputs. This is fixed for the known broken cases. Also, mux output
delays have been fixed. Also, release statements that apply to elided
nets are turned into no-ops.
The r-values of non-blocking assignments are now precalculated at
compile time, if possible, as is done with blocking assignments. This
speeds up constant propagation, and is more thorough.
Also optimize subtraction of small constants from vectors, with the
new %subi instruction in vvp. This saves some in code size and thread
footprint.
Handling of x in r-value bit selects and memory word selects did the
wrong thing. Now they do the right thing. Also, x in the selector of
?: ternary operators does the right (and complicated) thing now. In
the process, a fork-join code generator bug was fixed.
Several bugs with time formatting have been fixed.
Temporaries in sequential blocks are detected by the synthesizer, and
converted into wires when needed. This expands support for
combinational logic synthesis.
and if that doesn't exist look for /usr/libexec/cpp0. While here,
use ${X11BASE}/include instead of /usr/X11R6/include.
Should fix recently noted bulk build problems on 1.6 systems.
bug fixes: A couple of apertures drawn wrong has been fixed, like
lines with square apertures and rotation of aperture macro primitive 4.
new features: Zoom outline and the measurement tools. You can also export
the image as PNG,
Remove `-p' from mkdir arguments, it is already part of ${MKDIR}.
While here substitute a couple of ${PREFIX} by `%D' in
`@exec ${MKDIR} ...' lines and add a couple of missing `%D' in such lines too!
files. In addition sinclude the files 'site-config.inc',
'user-config.inc', and 'proj-config.inc' to allow for per-site, per-user,
and per-project configuration instead of only per-site configuration.
This is essential for use by non-sysadmin users and users who need to
keep project specific setups.
- remove all compiler warnings on alpha
- add ${PKG_SYSCONFDIR}/pcb/local.inc where admins can list site specific
libraries to be included instead of modifying one of the regularly
installed/deinstalled files. This way a local config is preserved when
the pkg is upgraded. Also a local config can be applied without modifying
one of the files which is checksummed during the install.
points to the magic installation. This avoids possible conflicts with
some other UCB tools which use CAD_HOME. Noted in private email from
Daniel Senderowitz.
Graphical quirks fixed are:
- zooming around the mouse pointer.
- zooming several steps at once goes much faster. No calculation and
redrawing in each zoom step, but in the last step.
When you click with the left mouse button on a layer button you
get a popup menu with color selection, load file and unload file.
That is on a "per layer-basis". The "global" "Open File..." menu is
removed in favor for this.
many improvements and bug fixes since the last packaged snapshot including:
-added the $sizeof system function as a builtin
-In VPI, the simulator event callbacks now work
-Concatenation expressions in parameters were broken are broken
-added the vpiModule iterator to VPI scope handles
Magic is an interactive system for creating and modifying VLSI circuit
layouts. With Magic, you use a color graphics display and a mouse or
graphics tablet to design basic cells and to combine them
hierarchically into large structures. Magic is different from other
layout editors you may have used. The most important difference is
that Magic is more than just a color painting tool: it understands
quite a bit about the nature of circuits and uses this information to
provide you with additional operations. For example, Magic has
built-in knowledge of layout rules; as you are editing, it
continuously checks for rule violations. Magic also knows about
connectivity and transistors, and contains a built-in hierarchical
circuit extractor. Magic also has a plow operation that
you can use to stretch or compact cells. Lastly, Magic has routing
tools that you can use to make the global interconnections in your
circuits.
Magic is based on the Mead-Conway style of design. This means that it
uses simplified design rules and circuit structures. The
simplifications make it easier for you to design circuits and permit
Magic to provide powerful assistance that would not be possible
otherwise. However, they result in slightly less dense circuits than
you could get with more complex rules and structures. For example,
Magic permits only Manhattan designs (those whose edges are vertical
or horizontal).
The most significant changes are the BJT model and "binning".
New features:
1. BJT model.
2. "Binning" for all MOS models.
3. Internal element: non-quasi-static poly-capacitor. (needed by BJT).
4. Enhancements to the data structures and model compiler to support
binning in general.
5. A line prefixed by "*>" is not ignored, in spite of the fact that
"*" usually begins a comment. This is a deliberate incompatibility
with Spice. If you prefix a line by "*>" it will be interpreted as a
non-comment in Gnucap, but a comment in Spice.
6. Circuit line prefixes of ">" and command prefixes of "-->" are
ignored. This is so you can copy and paste whole lines, without
having to manually remove the prompt string.
Changes that may or may not be improvements.
1. It is not the default to include stray resistance in device models.
The option "norstray" will revert to the old behavior. This is only a
change to the default value of "rstray".
Significant internal changes:
1. The internal element non-quasi-static poly-capacitor actually
works. It is used by the BJT model, and will eventually be used by
MOSFET models.
2. There are now two poly_g devices: "CPOLY_G" and "FPOLY_G". There
are interface differences that impact modeling. Previously, there was
only one, which is equivalent to the "FPOLY_G".
Release Notes for snapshot 20020317
The first difference in this snapshot from the 0.6 release is that vvm
is no longer compiled by default. If you want to compile vvm, you must
enable it at configure time (--enable-vvm) and rebuild from
scratch. Eventually, vvm will disappear from the release altogether.
The next major difference is new support for user defined
functions. It is new support, so it is bound to be buggy, but it
should be somewhat complete. The major problem has been solved, so all
that remains are bugs around the edges.
The vvp run-time scheduler has been changed slightly. The run time
behavior is getting increasingly precise and picky, as larger designs
are thrown at the compiler. The change introduced in this snapshot
fixes logic gates to not propagate zero-time pulses, and thus fixes
some weird bugs in large designs.
I've also added initial support for the Verilog 200x pragma comment,
which are (* *) pairs. For now, the compiler ignores them as
comments. This is what a compiler is supposed to do with anything that
is not specifically recognized.
Also, Tony (Anthony Bybell) has added LXT dump support. The LXT output
file is a waveform output format that is much more compact then VCD.
The gtkwave waveform viewer supports the LXT format, and should
operate a bit faster when viewing LXT files. For now, there are
separate system tasks for managing LXT output ($lxt_dumpvars, etc) but
eventually the dump format will be selectable by environment variable
or command line switch.
This snapshot also includes various random bug fixes and improved
error messages for incorrect code.
all dependencies on packages depending on "png" which contain shared
libraries, all for the (imminent) update to the "png" package.
[List courtesy of John Darrow, courtesy of "bulk-build".]
------
Atlc is a finite difference programme that is used to calculate the
properties of a two-conductor electrical transmission line of
arbitrary cross section. It is used whenever there are no analytical
formula known, yet you still require an answer. It can calculate:
The impedance Zo (in Ohms)
The capacitance per unit length (pF/m)
The inductance per unit length (nF/m)
The velocity of propogation v (m/s)
The velocity factor, v/c, which is dimensionless.
A bitmap file (usually with the extension .bmp or .BMP) of the cross
section of the transmission line is drawn in a graphics package such
as The Gimp and then analyzed using Atlc.
-----
Electric is a sophisticated electrical CAD system that can handle
many forms of circuit design, including:
Custom IC layout (ASICs), Schematic drawing, Hardware description
language specifications, Electro-mechanical hybrid layout
Electric has these CAD operations:
Design rule checking (3 options), Electrical rule checking,
Simulation and simulation interface (12 options), Generation (3 options),
Compaction, Compensation, Routing (4 options), VHDL compilation,
Silicon compilation, Network consistency checking (LVS),
Logical Effort analysis, Project Management
Electric handles these types of design:
MOS (6 CMOS variations, 1 nMOS variation), Bipolar and BiCMOS,
Schematics and printed circuits, Digital filters, Temporal logic, Artwork
Electric handles these file formats:
CIF I/O, GDS I/O, EDIF I/O, DXF I/O, SDF Input,
SUE Input, VHDL I/O, Verilog Output, EAGLE, PADS, and ECAD Output,
PostScript, HPGL, and QuickDraw output
only emit a message and don't actually fetch anything. This allows
us to make the output of "fetch-list" for these packages consistent
with other packages.
While we're in here, integrate DYNAMIC_MASTER_SITES with the
${ORDERED_SITES} macro. The only functional change here is that
${MASTER_SITE_OVERRIDE} is now respected. Still to do -- something
appropriate for "fetch-list" for these packages, like sourcing
"getsites.sh" into the generated script. (Well, "package", but there
are two others that do something similar in their "Makefile".)
Also eliminate the misbegotten _FETCH_ALLFILES macro -- now that only
"fetch" uses it, move it's functionality directly under "do-fetch".
* Don't declare a bunch of extern functions that are already declared by
system headers on NetBSD.
XXX This change may be incorrect for non-current systems.
Summary of changes:
- removal of USE_GTEXINFO
- addition of mk/texinfo.mk
- inclusion of this file in package Makefiles requiring it
- `install-info' substituted by `${INSTALL_INFO}' in PLISTs
- tuning of mk/bsd.pkg.mk:
removal of USE_GTEXINFO
INSTALL_INFO added to PLIST_SUBST
`${INSTALL_INFO}' replace `install-info' in target rules
print-PLIST target now generate `${INSTALL_INFO}' instead of `install-info'
- a couple of new patch files added for a handful of packages
- setting of the TEXINFO_OVERRIDE "switch" in packages Makefiles requiring it
- devel/cssc marked requiring texinfo 4.0
- a couple of packages Makefiles were tuned with respect of INFO_FILES and
makeinfo command usage
See -newly added by this commit- section 10.24 of Packages.txt for
further information.
Changes in Dinotrace 9.1g 01/24/2002
*** Reread all traces on receiving a USR1 signal. [Uwe Bonnes]
**** Allow value searches on one-bit signals. [Vitaly Oratovsky]
Changes in Dinotrace 9.1f 01/08/2002
*** Let right button terminate Zoom click. [Uwe Bonnes]
**** Fixed Emacs 21.0 incompatibility with back-annotation.
**** Hacked around bug causing window manager crash when
using Examine inside Zoom. [Uwe Bonnes]
* Changes in Dinotrace 9.1e 11/16/2001
*** Allow 1-bit wide signals to have statenames. [Dominik Strasser]
*** Eliminate common prefix from postscript dumps. [Dominik Strasser]
*** Show count of posedges and negedges in value examine.
WHAT'S NEW SINCE 0.5?
Quite a lot. Innumerable bugs have been fixed, and standards coverage
has been improved significantly. Warning and error messages have been
improved, and so has compile performance. Gate delays, strength
modeling, and floating point delays have all improved since the 0.5
release. If you had trouble with the 0.5 release, the 0.6 release
probably fixes your problem.
Support for large designs spanning multiple files has been improved
dramatically. The usual preprocessor inclusion method still works, but
The 0.6 release adds command files for keeping source file lists, and
automatic library searches for missing modules. The library mechinisms
are compatible with commercial tools, and commercial module libraries
can be used with Icarus Verilog.
Many compiler limitations related to the size and complexity of large
designs have been relaxed or eliminated. There are no known design
size limitations remaining in the compiler. Icarus Verilog should be
able to handle any design that you have the patience to compile.
A pkgsrc specific change is that it no longer conflicts with the
cad/spice package allowing both to be installed.
From the NEWS file:
This is a major release in terms of bug-fixes. Some enhancements
have been included: BSIM4 model and support for EKV model. The
source code for the latter must be obtained from EKV web site
(see DEVICE for more info). To enable EKV support you have
to obtain the code first and then use the configure switch
"--enable-ekv".
many many changes since the last packaged snapshot.
A brief sampling of the changes (which include many bug fixes and
enhancements) is:
A variety of little problems with $display format strings have been
fixed.
The % operand should now simulate properly. Also, the * operator is a
little bit more optimized, and works in constant expressions.
Several bugs in strength modeling have been fixed. This includes drive
strengths on continuous assignments, which in the past generated code
without the strengths. Also, vvp gained some missing support for
constants with strength. I think that strength modeling is now
complete.
vpi_get_vlog_info support has been added to the vvp run-time. This is
a PLI function that allows access to run-time command flags. Also, vpi
access to root modules now works properly.
changes since 0.0.5:
- Turn on and off explicit layers.
- Color on button reflect color on layer.
- Automatic detection of drill- or gerber file.
- Tooltips over buttons to reflect loaded filename.
- Handles Polygon Area Fill
- Major rehacking of file IO and pan code to significantly
increase speed.
- Autoscaling. Loaded gerber files are automagically scaled and
panned to fit in window. Also possible to do with loaded files
with Zoom/Fit meny option.
- configure.in enhancement to support package building in Red Hat.
Thanks to Wojciech Kazubski for patch.
- bzero changed to memset, which hopefully is more POSIX (for portability).
- Loads of bugs squashed and hopefully fewer added.
Many changes since the last packaged snapshot. A sampling of these are:
Support for hierarchical names has been largely rewritten. The major
consequence of this is that escaped names now have much better
support. By now, most any combination of escaped and hierarchical name
should work properly, for nets, parameters, and anything else.
Output delays for primitive gates, including user defined primitivies,
should now work properly. Delays on nets still do not work, although
the parser now parses them and prints a "sorry" message.
Bugs in support for division(/) and modulus (%) have been fixed.
Bugs in l-values of synthesized DFF devices have been fixed. These
bugs were related to part selects of vectors in l-values.
A few XNF code generator bugs and limitations were fixed.
And as usual, a variety of miscellaneous bugs have been fixed in this
snapshot.
The bit size of the results of some unary redunction operators is now
properly handled. Also, similar problems with logical functions have
been fixed.
force/release now works for variables, though not yet for
nets. Assign/deassign already work.
many other bugfixes
pkgsrc. Instead, a new variable PKGREVISION is invented that can get
bumped independent of DISTNAME and PKGNAME.
Example #1:
DISTNAME= foo-X.Y
PKGREVISION= Z
=> PKGNAME= foo-X.YnbZ
Example #2:
DISTNAME= barthing-X.Y
PKGNAME= bar-X.Y
PKGREVISION= Z
=> PKGNAME= bar=X.YnbZ (!)
On subsequent changes, only PKGREVISION needs to be bumped, no more risk
of getting DISTNAME changed accidentally.
Mcalc is a JavaScript based calculator for accurate microstrip
transmission line analysis and synthesis.
The electrical parameters may be determined from specified physical
parameters, or the physical parameters required to meet a given set of
electrical parameters may be found.
Much attention has been given to making mcalc the most accurate online
based calculator short of a full electromagnetic simulation.
GnuCap is a general purpose circuit simulator. GnuCap was
formerly known as ACS. GnuCap performs nonlinear
dc and transient analyses, fourier analysis, and ac analysis
linearized at an operating point. It is fully interactive and
command driven. It can also be run in batch mode or as a server.
The output is produced as it simulates. Spice compatible models
for the MOSFET (level 1-7) and diode are included in this
release.
Since it is fully interactive, it is possible to make changes and
re-simulate quickly. The interactive design makes it well suited
to the typical iterative design process used it optimizing a circuit
design.
Unlike Spice, the engine is designed to do true mixed-mode
simulation. Most of the code is in place for future support of
event driven analog simulation, and true multi-rate simulation.
If you are tired of Spice and want a second opinion, you want to
play with the circuit and want a simulator that is interactive,
you want to study the source code and want something easier to
follow than Spice, or you are a researcher working on modeling
and want automated model generation tools to make your job easier,
try GnuCap.
Gerber Viewer (gerbv) is a viewer for Gerber files. Gerber files
are generated from PCB CAD system and sent to PCB manufacturers
as basis for the manufacturing process.
The different layers of the PCB are separated into different files.
gerbv can load all files at the same time, though it can not show
them at the same time. You have to browse through the different layers
with the radio buttons on the right side.
redefines about which buildlink.mk files would care is BUILDLINK_X11_DIR,
which points to the location of the X11R6 hierarchy used during building.
If x11.buildlink.mk isn't included, then BUILDLINK_X11_DIR defaults to
${X11BASE} (set in bsd.pkg.mk), so its value is always safe to use. Remove
the ifdefs surrounding the use of BUILDLINK_X11_DIR in tk/buildlink.mk and
revert changes to move x11.buildlink.mk before the other buildlink.mk files.
changes since last snapshot include:
- addition of a fpga target for synthesis. outputs edif, optimized for
xilinx virtex parts.
- fixed bug with synthesis of !=
- fixed bug in hex constant parsing
- fixed vvp bug with subtracting very wide words
- much improved VCD output
- many other bug fixes and robustness improvements.
use X11_BUILDLINK_MK as a test value. Generally just reordering the
inclusions so that x11.buildlink.mk comes before the other buildlink.mk
files will make everthing work.
New in 20011020:
- better measurement: value at both cursors or difference in values at cursors
- enhanced handling of log scales
- yet more file-reading improvements and general bug fixes
foo-* to foo-[0-9]*. This is to cause the dependencies to match only the
packages whose base package name is "foo", and not those named "foo-bar".
A concrete example is p5-Net-* matching p5-Net-DNS as well as p5-Net. Also
change dependency examples in Packages.txt to reflect this.
Changes include:
- add the ability to specify gain in terms of voltage gain _or_ power gain
- add input/output resistance keywords
- add defaults keyword to allow users to change program defaults on the fly
- the cascade-mode for emacs now works for fontlock
- add voltage output levels in addition to the power levels
- add a verbose style comment (ie, one which gets copied to the output file
instead of being simply ignored).
- new homepage and master ftp site.
The previous version had no known bugs. Hopefully this one won't either.
to ${X11BASE} in the header and library search paths into references to
${LOCALBASE}/share/x11-links. These packages should now be strongly-
buildlinked regardless of whether xpkgwedge is installed.
Changes well-tested on NetBSD-1.5X/i386 with and without xpkgwedge and
lightly-tested on NetBSD-1.5.1/alpha without xpkgwedge.
* The Big Change: VVP
Past versions of Icarus Verilog performed simulation by compiling the
Verilog design to intermediate C++ code, then in turn compiling that
C++ (usually with G++) to a binary executable. This program was then
executed to actually run the simulation.
The 0.5 compiler, however, uses a custom internal language called
"vvp." The vvp code generator writes a program in the vvp language
that the vvp interpreter executes. This gets runtime performance
similar to the older vvm method, but compile times are much faster.
The result of this change is that there is a new program, ``vvp'',
that is installed with the existing ``iverilog'' compiler. This
program actually executes the simulation generated by the vvp code
generator.
There are manual pages for the iverilog command and the new vvp
command, as well as a QUICK_START document to help you run your first
simulation.
* What Else Is New
The compiler itself is now a lot more robust. While it still does not
compile and understand the entire IEEE1364 standard, the compiler is
less likely to crash on bad input, gives better error messages, and
has generally been cleaned up.
------------------
ACS 0.29 release notes (06/30/2001)
The primary effort has been to implement IBIS, which is still not
done. The changes here are mostly infrastructure changes needed to
support IBIS.
New features:
1. "Fit" function has choice of fit order and extrapolation. You can
have order 0, 1, 2, or 3.
2. "Posy" has even and odd options, to determine what happens in the
negative region.
3. Modelgen improvements. It now is useful for the whole device,
sometimes. It now handles probes and the device side of the model.
The diode uses it completely. There are still a few missing features
needed for the MOSFET and BJT.
4. Spice-3 compatible semiconductor resistor and capacitor.
5. "Table" model statement.
Improvements, bug fixes, etc.
1. Option "numdgt" really works.
2. Better error messages from modelgen.
3. Code changes for optimization of commons. This should reduce
memory use, sometimes, by sharing commons. Common sharing is still
not fully implemented.
4. Fix two bugs that sometimes caused problems after a "modify" or on
a "fault".
5. Better handling of "vmin" and "vmax". It should be much less
likely that limiting causes convergence to a nonsense result.
Some things that are still partially implemented:
1. Internal element: non-quasi-static poly-capacitor.
2. BSIM models, charge effects, "alpha0" parameter. (computed then ignored)
changes are:
-----------
RELEASE NOTE FOR ICARUS VERILOG 20010630
I've done some cleanup of the mingw port of Icarus Verilog. I've also
added instructions for how to build Icarus Verilog under mingw. I'm
working on making that the preferred way to support Windows, and when
I make the 0.5 release I will make Windows binaries this way. Anyhow,
feedback on the build instructions and the build results using the
instructions in mingw.txt are welcome.
I've make "vvp" the default target type. The older vvm behavior is
available with the "-tvvm" flag to iverilog, but I would rather be
told about (and fix) bugs in the vvp code generator and run time.
I've added support for the (unsigned) right shift operator. The left
shift has been working for a while now, but right shift somehow
slipped through the cracks. The shift operators still don't quite work
in structural contexts, but they should show up sometime next week.
I've finally got VCD output working properly with vvp. It may even be
better then with vvm, although some internal symbols are still generated.
A few odd bugs have been fixed, including a code generation error for
xnf, and error checking of user defined function parameters.
CXXFLAGS, and LDFLAGS by the buildlink.mk files so remove the extra
definitions to add them from the package Makefiles. As advised by the
bsd.buildlink.mk file, also ensure that the buildlink.mk files are
included prior to defining any package-specific CFLAGS/LDFLAGS to ensure
that the buildlink directories are at the head of the compiler search
paths.
Use BUILDLINK_INCDIR, BUILDLINK_LIBDIR for locations of linked headers
and libraries. Create a variable BUILDLINK_TARGETS whose value is the
list of build-link targets to execute.
(2) Use devel/readline/Makefile.readline to get readline support, and note
why GNU readline is required.
(3) Make this package work with xpkgwedge...the app-defaults file was
always being installed under ${X11BASE}.
many changes since the last snapshot. Mostly they involve expanded
VVP support. The VVP target now passes >200 of the tests from the
test suite. While not as complete as the VVM target, VVP is getting
closer and its _much_ _much_ faster.
increase in version number. From the XCircuit homepage:
Note that the March 28, 2001 version corrects a bug due to
dubious C syntax causing segmentation violations when xcircuit
was compiled without the debug option.
C Trivia question:
What does "x[a] = x[--a]" do?
Answer A: "x[a] = x[a - 1]; a--"
Answer B: "a--; x[a] = x[a]"
Answer C: either A or B, depending on your OS, compiler version,
and/or debug or optimizer switch.
Changes since the last packaged snapshot from the authors announcements:
Icarus Verilog snapshot 20010422
--------------------------------
I've integrated a bunch of UDP patches from Stephan Boettcher. These
go to the core of ivl, so if you use Icarus Verilog with UDPs, you
might want to give this a test for us.
Stephan has also added some ivl_target support for UDP devices. This is a
prerequisite to vvp support for UDP devices.
Some of you have been beating me over the head about disable, so the
vvp target now supports disable. It only works in certain very constrained
situations, but the idea is there and the more common cases are simply a
matter of getting around to them. I actually could use more examples of
the use of disable for the test suite.
In the process, I have settled on the interaction of threads and scopes,
and changed the %fork syntax to match. See the README.txt and opcodes.txt
file for details. The implementation of %end and %join simplified in
the process.
The vvp-tgt code generator supports a few more gate types. New gate
types are pretty easy to add, it's just boring grunt work. That's why
they've been popping up slowly.
I've also got certain behavioral shifts working. Only constant shifts,
so far, but this covers a pretty large percentage of the real world
uses of shift, I think.
I fixed a few specify block parse problems, so it should ignore
even more complex specify blocks now:-) One of these days I really will
properly support specify blocks.
PROGRESS
I was hoping to get vvp up to a similar level as vvm by the end of
April, but that doesn't look like it's going to happen. I'm up to 182
tests passed, compared to 318 of Icarus Verilog/vvm, so I have a ways
to go yet. I see no real point to making a release until I get up to
300 or so tests passed. That is the goal for 0.5 release.
But of course if vvp is enough for you, then it is soooo much faster
then vvm.
Icarus Verilog 20010415 Snapshot
--------------------------------
As with all the most recent snapshots, this is almost entirely progress
with the vvp code generator and simulation engine. I'm up to 159 tests
passed in the test suite, so I'm getting there. But there's still plenty
to go.
I also fixed what appeared to be a minor problem with elaboration of ?:
expressions in continuous assignments. The code was actually fine, it
was a spurious assert. This fix affects vvm as well.
Icarus Verilog/vvp now support <= statemements with internal delays.
That is, "foo <= #10 bar;" should work properly, and there are tests
in the suite that prove it. This is a pretty common syntax, so this
should help a lot of folks.
I also fixed a bug in the code generator that would cause it to put a
constant bit as a destination for the bitwise boolean operators. This
caused run-time asserts.
The event or support in vvp has been extended to now support arbitrary
width, so now you can for example wit for any changes in a 32bit reg.
This handles most of the likely cases, so @ statements should now be
pretty generally functional.
The handling of run-time threads has been revamped in preparation for
support of the disable statement. It also plugs a memory leak where
fork/join and task/function calls are invoked. And this version should
also clean up all those tiny initial foo=bar threads that all programs
seem to have. Threads that are done are now freed, along with their
memory, hopefully reducing the runtime memory footprint.
That's pretty much it this time 'round. Working with threads took some
time, so the progress isn't as flashy as it sometimes is.
There is still lots to do with vvp before 0.5, but I would appreciate
any feedback you can offer. It's complete enough already that I'm able
to accept bug reports on it, even if it turns out to be a "not supported
yet" type of thing. At this point, I'd be curious to know what hangups
are preventing its regular use.
Surface Impedance Method for Interconnect Analysis.
SIMIAN is a two dimensional frequency dependent series
impedance extraction tool for inerconnects and transmission
lines using conductors of rectangular or circular cross section.
The use of the surface ribbon method (SRM) greatly enhances
the speed of computation relative to the volume filament
method (VFM).
* Control Panel
- The Control Panel now has a "Tree View" which provides an
overview over all areas of EAGLE, like Libraries, User Language
Programs, Projects etc. The Control Panel's tree view supports
"Drag&Drop" to copy or move files and directories.
- Objects in the tree view have a context menu that can be
accessed by pressing the right mouse button.
- The menu option "Save project as..." is no longer available.
- New projects can now be created via the context menu in the
"Projects" tree item, or by selecting "File/New/Project" from
the Control Panel.
- The path settings in "Options/Directories" can now use the special
names "$HOME" and "$EAGLEDIR" to access the user's home directory
or the EAGLE installation directory, respectively.
- The new "Auto backup" feature will automatically save any modified
drawing into a safety backup file after a certain time.
* New Project Structure
- The names of files that are under the current project directory
are no longer written as absolute paths into the 'eagle.epf' file,
but rather relative to the project directory. This allows for
complete project directories to be easily copied or renamed.
- A project is now held in a subdirectory that contains a file
named 'eagle.epf' (which stores the location and settings of open
windows).
* User Interface
- The textual command menu can now be configured to display
aliased command buttons as well as submenus (see HELP MENU for
details).
- Changes made in the "Options/User interface" dialog now take effect
immediately for open editor windows.
- The cursor inside a layout or schematic editor window can now be
set to a "large" crosshair cursor (see "Options/User interface").
- The "Delete" icon was changed from a pencil with an eraser to
an 'X'.
- The "Split" icon was changed to better indicate what will happen.
* Keyboard and mouse control
- Alt-0 no longer popups up the window list, but leads directly to
the Control Panel.
- Pressing the Ctrl key while moving the mouse now scrolls the draw
window in any direction.
- The mouse wheel now zooms in and out in editor windows (zoom
factor can be adjusted in "Options/User interface/Mouse wheel
zoom", a value of '0' disables this feature and the sign of this
factor defines the direction of the zoom operation).
* Screen display
- The default for "minimum visible text size" has been changed to 3.
- The display mode parameter FAST has been dropped.
- By default the zoom factor in editor windows is limited so that
the resulting virtual drawing area does not exceed the 16-bit
coordinate range. This is necessary to avoid problems with
graphics drivers that are not 32-bit proof. If the graphics
driver on a particular system can handle coordinates that
exceeed the 16-bit range, "Options/User interface/Limit zoom
factor" can be switched off allow larger zoom factors.
* Design Rules
- EAGLE now supports a full set of Design Rules that are stored
inside the board file (and can also be saved to disk files).
Both the Design Rule Check and the Autorouter will use the
same set of rules.
- Newly created boards take their design rules from the file
'default.dru', which is searched for in the first directory
listed in the "Options/Directories/Design rules" path.
- Cream mask values are now measured "inwards" and thus have a
positive sign.
- The parameters AnnulusConduct and ThermalConduct are no longer
available. There are now checkboxes in the Design Rules dialog's
"Supply" tab that define whether a Thermal or Annulus symbol
shall have a "Restring" or not.
* Net Classes
- Nets and Signals now have a new parameter called "Net Class".
* Polygons
- When calculating polygons, the minimum distances defined in
the design rules and net classes will be taken into account.
* Design Rule Check
- The DRC now runs a lot faster.
- Progress is now displayed in a progress bar.
- Polygons from different signals with the same 'rank' are checked
against each other.
- The 'overlap' and 'minimum distance' check are no longer separate
checks.
- The DRC no longer checks an individual signal against everything
else. The newly introduced "Net Classes" can be used to do this.
- The rectangle for a selective DRC can now be defined with
"click&drag" (just as in the WINDOW command).
- Holes are no longer checked in the "Grid" check (only pads, vias,
smds and wires in signal layers are checked).
- Any objects in signal layers within a package are now checked
against each other.
* Long strings
- All names, values and texts can now be of any length.
- The User Language constants regarding name lengths still exist,
but the program uses these constants only for formatted output as
in the EXPORT command. They are still present for compatibility
only.
- There is no more limit to the number of members in a bus (bus
index values are limited to 0..511).
- Bus member names can now contain any characters, except
':', ',', '[', ']' and blanks.
* Wire styles
- Wires now have a new parameter 'Style', which can be set to one
of the following values:
Continuous _______________ (default)
LongDash ___ ___ ___ ___
ShortDash _ _ _ _ _ _ _ _
DashDot ___ . ___ . ___
- The variable for setting the bend type of a wire has been renamed
from Wires_Style to Wire_Bend to avoid confusing the two
parameters.
* Text fonts
- Texts can now have three different fonts: 'Vector' the program's
internal vector font (as used in previous versions)
'Proportional' a proportional pixel font (usually 'Helvetica')
'Fixed' a monospaced pixel font (usually 'Courier')
- When updating drawings from older versions, all texts are
converted to 'Proportional' font, except for those in layers
Top...Bottom, tRestrict and bRestrict, since these texts probably
need to be subtracted from signal polygons, which only works with
the 'Vector' font.
- The program makes great efforts to output texts with fonts other
than 'Vector' as good as possible. However, since the actual font
is drawn by the system's graphics interface, 'Proportional' and
'Fixed' fonts may be output with different sizes and/or lengths.
* Pads and Vias
- The diameter of pads and vias is now derived from the drill
diameter using the Design Rules (the pad and via diameter '0' is
now allowed and results in a diameter that is derived from the
current design rules). If a pad is defined with a diameter that
exceeds the one that would result from the current design rules,
the larger diameter is taken. The default value for the diameter
of newly created pads and vias is now '0' to allow the Design
Rules to define the actual diameters.
- Pads can have different shapes on Top and Bottom (they will always
be 'round' on the inner layers).
- The via shape now only applies to the outer layers (they will
always be 'round' on the inner layers).
- The diameter of pads with shape X/YLongOct now defines the
smaller side of the pad (formerly the wider side). Existing
files will be modified accordingly during the update.
- By default vias no longer generate Thermal symbols in supply
layers.
* Round SMDs
- SMDs have a new parameter "Roundness", which can range between
0 and 100 and defines the percentage by which the corners are
"rounded". A value of 0 (default) results in a rectangle, while
a value of 100 results in a circular shape (if the x and y
dimension of the SMD are the same), which can be used for BGAs.
- The SMD command accepts roundness values as numbers with a
leading '-' (to be able to distinguish it from the SMD size
values). The CHANGE command has a new option "Roundness".
* New Library structure
- What was called a "Device" in previous versions is now
called a "Device Set". A "Device Set" consists of the gate
definitions and several actual devices, implemented through
"Package Variants"
- The PACKAGE command can now assign several different package
variants to a device (as in 7400N, 7400D,...).
- The new command TECHNOLOGY can be used to define various
"technology" variants for a device's package variants (as in
74LS00N, 74S00N,...).
- The CHANGE command has the new options PACKAGE and TECHNOLOGY,
which can be used to select from the packages and/or technologies
a device set defines. This can be done from within the schematic
or board.
- The new command DESCRIPTION can be used to provide detailed
textual information about a device, package or library.
- The CONNECT dialog now allows copying pin/pad connections from
an other package variant. Only those package variants are offered
in the "Copy from" combo box that have the same pad names as the
current package variant (only connected pads are checked).
- The CONNECT dialog now asks the user if he want's to discard
any changes before cancelling the dialog.
- The CONNECT command can now handle gate names that contain
periods.
- The device editor now displays a list of package variants, a
preview of the current package and the description of the
device.
* Automatic Library update
- If a library has been modified after parts or packages from it
have been added to a schematic or board, the new command UPDATE
can be used to automatically update all used library objects with
their latest version (see "Help Update").
- The UPDATE command can be selected from the "Library" pulldown
menu in a board or schematic, or from the context menu of a
library in the Control Panel. It is also possible to drag&drop
a library from the Control Panel onto a schematic or board
drawing and perform the update that way.
* Bill Of Material
- The User Language Program 'bom.ulp' to generate the "Bill Of
Material" has been rewritten. It now has a dialog in which the
user can interactively generate the BOM, pulling in additional
data from a user defined database file. Use "RUN bom.ulp" and
click on the "Help" button for more information.
* Generating Outlines for milling prototypes
- The User Language Program 'outlines.ulp' can be used to generate
the data necessary to control a milling machine for generating
a prototype board.
* User Language
- The User Language now supports user defined dialogs as well as
standard file dialogs and message boxes.
- The RUN command now accepts additional arguments that are
available to the ULP as 'argc' and 'argv' parameters.
- Data can now be read into a ULP.
- The new lookup() function can be used to perform database
lookups.
- The new fileglob() function can be used to do a directory
search.
- The new fileerror() function can be used check for I/O errors.
- The 'exit()' function can now have a string parameter which is
sent to the editor window and executed as a command string.
- ULPs can now include other ULP files with the new #include
directive.
* Script files
- Script files can now call other scripts (as long as no
recursive call is made).
- Script files can now contain comments. Everything after
(and uncluding) a '#' character will be ignored.
- The 'eagle.scr' file is now first searched for in the current
project directory (which is equal to the current working
directory in case there is no project open) and then in the
directories listed in the Control Panel's
"Options/Directories/Scripts".
* Autorouter
- The Autorouter can now route "through" signal polygons (this
can be controlled by the new cost factor 'cfPolygon').
- The Autorouter control parameters are now stored inside the
board file. They can be saved to and loaded from external files
via the Autorouter dialog. Existing control files will be
automatically read and stored in the board file when updating
files from previous versions.
- The Autorouter and DRC now use the same set of Design Rules.
- When saving Autorouter control parameters to disk, the minimum
distance parameters are no longer part of that file.
- There can now be any number of 'Optimize' passes. By default
there are now 4 'Optimize' passes.
- Each pass can be separately activated or deactivated.
- The Autorouter can now route different wire widths and minimum
distances simultaneously by using "Net Classes".
- The minimum routing grid is now 0.02mm (about 0.8mil).
- The default control parameters and the internal handling of
cfChangeDir have been modified to avoid jagged tracks.
* ADD command
- The ADD command can now be used with wildcards ('*' or '?') to
find a specific device. The ADD dialog offers a tree view of
the matching devices, as well as a preview of the device and
package variant.
- To add directly form a specific library, the command syntax
ADD devicename@libraryname
can be used. 'devicename' may contain wildcards and
'libraryname' can be either a plain library name (like "ttl"
or "ttl.lbr") or a full file name (like
"/home/mydir/myproject/ttl.lbr" or "../lbr/ttl").
- If a device or package shall be added, and there is already
such an object (with the same name from the same library) in the
drawing, an automatic library update will be performed which
replaces the existing object in the drawing with the current
version from the library.
- The new command UPDATE can be used to update all parts in a board
or schematic with modified library versions (see "Help Update").
* CHANGE command
- CHANGE LAYER for wires and polygons now works between any
layers within packages and symbols.
* CONNECT command
- Pressing the SPACE key in the CONNECT dialog while a list element
has the focus will now perform the 'connect' or 'disconnect'
action, respectively.
* DELETE command
- If the last supply symbol of a given type is deleted from a net
segment that has the same name as the deleted supply pin, that
segment is now given a newly generated name (if there are no other
supply symbols still attached to that segment) or the name of one
of the remaining supply symbols.
* DISPLAY command
- The new parameters '?' and '??' can be used to control what
happens if a layer that is given in a DISPLAY command does not
exist in the current drawing. See "Help Display" for details.
* GROUP command
- If the selected group is empty, the GROUP command no longer
displays a message box saying "Group is empty". It rather prompts
that message in the status bar (with a beep) and stays active for
a new group definition.
* ERC command
- The ERC now lists the package names when reporting parts/
elements with inconsistent packages.
- The ERC now detects inconsistencies between the implicit power
and supply pins in the schematic and the actual signal
connections in the board.
- The ERC now checks for missing junctions and overlapping wires
and pins.
* ERRORS command
- The ERRORS dialog is no longer modal (it stays "on top" of the
editor window) and can be kept open while resuming normal
editing in the editor window. The various error types are now
listed more detailed.
* EXPORT command
- The EXPORT can now export image files (BMP, PNG, etc.). See
"Help/EXPORT" for details.
* NET and BUS command
- If a net wire is placed at a point where there is already
another net or bus wire or a pin, the current net wire will be
ended at that point (in previous versions the user had to click
twice to end a net wire).
* PASTE command
- When pasting objects into a drawing that already contains earlier
(different) versions of these objects, an automatic library
update will be performed which replaces the existing objects in
the drawing with the new versions from the paste buffer.
* PRINT command
- The PRINT dialog's "Page setup" now allows border values that
are smaller than the initial values derived from the printer
driver. To get back to the original default you can enter '0'.
* REMOVE command
- The REMOVE command can now handle device, symbol and package
names with extension (for example REMOVE name.pac).
* RENAME command
- The RENAME command now allows '.' in names.
- The RENAME command can now handle device, symbol and package
names with extension (for example RENAME name1.pac name2[.pac]
- note that the extension is optional in the second parameter).
* REPLACE command
- The REPLACE command can no longer be used with active forward-
and backannotation. This is due to the now complete definition
of a device set with all its package variants. Use the CHANGE
PACKAGE command to select one of the defined package variants,
or use the UPDATE command to update a package with a modified
version from the same library.
* SET command
- The SET options for Thermal and Annulus parameters as well as
the Solder Stop and Cream mask data have been removed.
- The SET variables DRC_SHOW and DRC_COLOR are now obsolete
(progress in the Design Rule Check is now displayed in a
progress bar).
- The SET variable MAX_ERROR_ZOOM is now obsolete. The ERRORS
dialog is no longer modal (it stays "on top" of the editor
window) and zooming can be done with the usual WINDOW commands
or buttons.
* SHOW command
- Highlighted objects are now kept highlighted during subsequent
window operations.
- Pressing ESCape in the SHOW command now lowlights the currently
highlighted object.
* USE command
- The USE command is now mainly for use in script files.
* CAM Processor
- The CAM Processor no longer supports matrix printers. Use the
PRINT command to print to the system printer.
- The CAM Processor no longer prints sheets. Use the PRINT
command instead.
* Parameter storage
- User specific parameters are now stored in an "eaglerc" file.
At program start, parameters are read (in the given sequence)
from the files
prgdir/eaglerc
/etc/eaglerc
$HOME/.eaglerc
where prgdir means the directory that contains the EAGLE program
file.
* Command line options
- The options '-A' and '-T' are now obsolete (thermal and annulus
data is now defined in the Design Rules).
- The options '-B' and '-M' are now obsolete (solder stop and
cream mask data is now defined in the Design Rules).
- The option '-C' is now obsolete, since the CAM Processor no
longer supports matrix printers (all printing is done with the
PRINT command).
- The options '-Z' and '-Y' are now obsolete (drill symbols are
configured in "Options/Set/Drill" and are stored in the user
specific "eaglerc" file).
* Miscellaneous
- The DOS and OS/2 platforms are no longer supported.
- Due to changes in the file data structure you will most likely
be asked whether to run the ERC when loading a board/schematic
pair created with an earlier version of EAGLE.
- Files from earlier versions of EAGLE may contain library objects
with the same names. This was caused by PASTE or ADD operations
with modified devices or packages. Version 4 no longer allows
this to happen, and therefore needs to make sure updated files
do not contain multiple objects with the same name. In order to
assure this, the update routine adds the '@' character and a
number to the names of such library objects.
- The library editor can now edit devices and symbols, even if the
user's license does not contain the schematic module.
- Avoiding multiple 'Save?' prompts for boards and schematics that
are connected via f/b annotation.
- When a file is modified while updating from a previous version
the resulting update report is now presented in a separate text
window.
Microstrip Patch Antenna Calculator. MPAC analyzes various parameters
including impedance and resonant frequency for a rectangular microstrip
patch antenna.
changes since last snapshot are (from the authors email)
verilog-20010407
--------------------
Still more progress on the new VVP simulation engine:
As with last week, this snapshot includes a lot of work on the ivl_target
API in support of code generation for vvp. Also, the vvp execution engine
has progressed some.
In fact, vvp has grown up to understand signed vectors and some signed
expressions. The signed vectors are mostly for VPI use, the signed
comparison instructions actually do signed work. Case comparisons are
new, along with %and and %or instructions, and %nor/r for reduction.
I also added a few new gate types to the .functor support.
A bug in the propagation of values by %set instructions has been fixed.
Specifically, the %set instruction not only sets the value of the .var
that it references, but also executes the propagation events that result.
This fixed some event ordering bugs.
Some VPI support needed by system.vpi is added to vvp to allow it to
properly handle signed signals, decimal values, and a few other details.
$display should work much better then it did last week.
Back in the vvp.tgt code generator, lots of new stuff is happening.
Several of the bitwise binary operators have been added, as well as
more comparison operators. This includes handling of signed expressions.
This also implies that vvp.tgt generates the proper .net vs .net/s
and .var vs .var/s statements.
User defined functions and tasks are now working. In fact, the vvp
target probably handles more functions (in behavioral code) then the
vvm engine. I've received several bug reports about user defined functions
with loops, that don't work under vvm. These should work with vvp.
Non-blocking assignments now work, too.
All forms of case/casex/casez are supported by the code generator, and
use the proper compare instructions. Forever, Repeat and While loops
also work now. A few bugs in event handling, and all the edge types
(including behavioral triggers) should work with limitations. Event or
is still in the works, and any-edge of large vectors (>4 bits) does not
work.
*Whew!*
As you can see, a *lot* of stuff is happening. I'm up to passing 110+
tests in the regression test suite (Icarus Verilog/vvm passes 318 tests)
so the changes are actually making things work. Test and be merry!
verilog-20010331
--------------------
More and more progress on VVP. More and more snapshots.
A lot of work has been done to the ivl_target loadable target API.
This API is growing to support the also growing tgt-vvp target. I've
added support for case statements, event triggers fork blocks.
Of course this also means that the tgt-vvp code generator and the
vvp simulator now support constructs including case, events, and
parallel blocks.
I've also fixed up the driver to properly report errors that tgt-vvp
detect. This makes the test suite regression script work a lot better.
I'm up to more then 70 tests in the test suite passing. I'm finding
that writing the code generator for vvp assembly is a *lot* easier
then writing a code generator for C++/vvm. Fortunately, the vvp
assembler is pretty fast.
At any rate, the vvp simulation engine is starting to show signs of
being useful. It still does not cover nearly as much of Verilog as
vvm, but what it does cover is so much faster that it may be worth
your while to try it out. And more eyes looking at it can only be a
good thing.
the authors announcement are:
There are a few bugs in the main compiler that are fixed. There has
also been an extension to the $fopen that adds support for opening
files for reading. The $fgetc has been added to take advantage of this.
This was done on the VPI side, although a slight extension to the mcd
functions was created.
The real news is the vvp simulation engine. I've added the tgt-vvp
code generator source and the vvp assembler/simulator, and the combination
actually produces the occasional working program. And it makes them
very quickly. So far as I can tell now, I am going to be very pleased
with the final outcome when this work is complete. However, it is not
at all ready to use. This snapshot is mostly to give a preview of things
to come to a wider audience.
HOW VVP WORKS
If you are accustomed to the existing vvm behavior, you remember that
the vvm simulator works by generating C++ and feeding that to the g++
compiler. Many of you are painfully aware of that.
VVP does *not* work like that. Instead of generating C++, the
generator emits assembly language for an abstract simulator processor.
The processor that the assembly targets doesn't really exist, but the
vvp program, included in this Icarus Verilog snapshot, assembles the
code to data structures in memory, then efficiently emulates the abstract
processor.
So the simulation of a program via vvp works by first compiling the
Verilog to vvp assembly. The vvp.tgt modules generates the code, and
is envoked when you use the ``-tvvp'' switch to iverilog.
The vvp assembly file so created is then passed to the vvp program to
be assembled and executed. There is a single vvp input file that is the
design to simulate. The vvp assembler is designed to execute the design
efficiently.
HOW TO LEARN MORE
The ivl_target.h header file describes the loadable target API that
the vvp code generator uses to gain access to the design. Then the
tgt-vvp directory contains the implementation of the vvp code generator.
The vvp directory contains the implementation of the assembler/simulator
that runs the compiled design. The README.txt file describes how the
vvp program works in general, and points to other txt files. There are
a variety of other .txt files in the vvp directory that describe how
the major components of the vvp program work.
first component is now a package name+version/pattern, no more
executable/patchname/whatnot.
While there, introduce BUILD_USES_MSGFMT as shorthand to pull in
devel/gettext unless /usr/bin/msgfmt exists (i.e. on post-1.5 -current).
Patch by Alistair Crooks <agc@netbsd.org>
QCad is a simple 2D CAD System. With QCad you can easily construct and
modify drawings with ISO-texts, dimensions, hatches and many other
features and save them as DXF-files. These DXF-files are the interface
to many CAD-systems such as AutoCAD and many others.
While here, update MASTER_SITE.
changes from last packaged version:
* Changes in Dinotrace 9.1b 2/13/2001
**** Documentation updates.
* Changes in Dinotrace 9.1a 1/22/2001
** Added analog waveform format. [Dave Colson]
Includes new Signal Waveform menu and signal_waveform command.
* Changes in Dinotrace 9.0m 11/21/2000
**** Fixed a bug reading compressed tempest on Digital UNIX. [Steve Hoover]
up a possibly out of date installed header from ${LOCALBASE}/include.
Note that while we don't support installing a pkg when a previous version
is installed, we should still be able to build it.
Problem noted in private email from Lennart Augustsson.
from the authors announcement:
So many things have changed since version 0.3 that there is no point
in listing them. There have been tons and tons of bug fixes and the
language coverage is better, and so on and so forth. It's just so very
much better then version 0.3:-)
speaking as a user, some of my personal favorites are:
- support for signed variables
- iverilog now gives correct return codes (which makes 'make' much happier)
for a more complete list, the commit messages for
pkgsrc/cad/verilog-current/Makefile contain the changes for each
development snapshot between verilog-0.3 and verilog-0.4
considered stable. Xcircuit now has the ability to pass parameters
to objects. For the moment, this only works with string parameters.
Integral parameters will be added in upcoming versions.
bug fixes and signed support (yay!).
detailed changes since last packaged snapshot from the
authors announcements:
Icarus Verilog snapshot 20010113
--------------------------------
We're getting close to release candidates. Maybe another snapshot, then
I start with making 0.4 release candidates. So lets get this tested so
that I can move forward!
This snapshot largely fixes a whole bunch of bugs. I'm working feverishly
to catch up to the reported bugs, but they are coming in about as fast
as I can resolve them. (Not that I'm complaining, mind you. These PRs
are really helping me make it better.) But that means I'm going to just
concentrate on getting as many PRs done as I can before the release.
The syntax of functions and tasks has been expanded to allow parameters.
This is not a common thing to do, but someone puts parameters if functions
The syntax of functions and tasks has been expanded to allow parameters.
This is not a common thing to do, but someone puts parameters if functions
so I had a PR to fix:-) Also I caught a problem with executing functions
that take no input parameters. In fact, a bunch of function related bugs
were fixed. I lost track of em all.
Ports of tasks weren't elaborated properly. I fixed this and a few related
problems so most legal l-values should work as task port expressions now.
Memories within tasks should also work properly now.
Speaking of ports, I now report errors when there is a port direction
for module ports that don't exist. In fact, there are a whole bunch of
cases where I've added required error messages.
The %d format of display strings now displays signed negative values as
negative values instead of the unsigned equivalent. This goes along with
the other signed arithmetic features from the -2000 standard that are now
supported.
I fixed up the Makefiles (thanks to a contribution) to support build using
the VPATH capabilities of the makefile. You should be able to compile for
multiple targets now from a shared source directory.
Icarus Verilog snapshot 20010106
--------------------------------
I'm just managing to barely keep up with the bug reports arriving in
the bug tracking system. I'm pleased with the success of the ivl-bugs
robot. These bug reports have allowed me to better manage and record
progress. Keep those bug reports coming!
I've added support for arrays of integer and time variables, as well
as the Verilog 2000 initialization syntax for these types. I have also
made some internal changes to integer support. Integers are now just
a shorthand for ``reg signed [31:0]'' and signed variable support has
made some internal changes to integer support. Integers are now just
a shorthand for ``reg signed [31:0]'' and signed variable support has
been generalized. This makes it easier on the code generators, as they
do not need to know that a variable was a integer, a time, a foo or a bar.
I few constant propagation errors have been fixed. Continuous assignments
of constants to nets should behave correctly now.
Many people noticed lack of expression support for parameters. In fact,
the problem was a lack of support for a bunch of specific operators. I've
added many operators. This has the side effect of improving constant
propagation as well, in some cases finding more dead code to eliminate.
This also affected expressions that were index expressions of memories
and vector declarations.
The / operator in continuous assignment expressions is fixed. There were
a few size related issue here that are now fixed.
I've added to the i3331364-notes.txt file a clarification of my position
on parse of repeat statements. This position is compatible with XL behavior.
Passing parameters to user defined functions in behavioral code was pretty
darn broken. I managed to fix this. You can tell that not many people use
user defined functions:-) (It doesn't help that Icarus Verilog is picky
about them.)
For vvm, I've put some effort into optimizing the compile time of programs
by reducing the size of the output code. I've reduced redundancies some,
and used loops to handle vectors where possible.
A few bugs related to $dumpvars were cleaned up. Function scopes work.
out of date - it was based on a.out OBJECT_FMT, and added entries in the
generated PLISTs to reflect the symlinks that ELF packages uses. It also
tried to be clever, and removed and recreated any symbolic links that were
created, which has resulted in some fun, especially with packages which
use dlopen(3) to load modules. Some recent changes to our ld.so to bring
it more into line with other Operating Systems also exposed some cracks.
+ Modify bsd.pkg.mk and its shared object handling, so that PLISTs now contain
the ELF symlinks.
+ Don't mess about with file system entries when handling shared objects in
bsd.pkg.mk, since it's likely that libtool and the BSD *.mk processing will
have got it right, and have a much better idea than we do.
+ Modify PLISTs to contain "ELF symlinks"
+ On a.out platforms, delete any "ELF symlinks" from the generated PLISTs
+ On ELF platforms, no extra processing needs to be done in bsd.pkg.mk
+ Modify print-PLIST target in bsd.pkg.mk to add dummy symlink entries on
a.out platforms
+ Update the documentation in Packages.txt
With many thanks to Thomas Klausner for keeping me honest with this.
Changes since the last packaged snapshot are (from the authors announcements):
Icarus Verilog snapshot 20001216
--------------------------------
This is the last snapshot before the holidays, so I hope it has your
favorite present in it. A lot of PR#s have been dealt with, and for a
brief moment I felt like I was getting ahead of the pending list:-)
I've added support for non-integer times, at least in a few contexts.
The `timescale directives should interact properly with the decimal
point in delays, causing more accurate timing simulations. This should
make vendor-supplied libraries work much better.
I've added support for signed reg variables. Signed expressions should
now generally do the right thing, but this feature needs much more testing,
and many more tests in the test suite. However, I do know that signed
comparisons should work properly. Bug reports for problems with signed
arithmetic are encouraged.
Many people have been having troubles with Cygwin compilation. The
problem was with the latest version of binutils. Venkat came up with a
solution that works with old and new binutils, so you can now compile
with the very latest cygwin software. This should make things a lot
easier for a lot of people.
I've made initial steps toward an HP/UX port. The configure script should
detect the right dl library to use, and the t-dll target should be able
to load loadable targets. I am looking for a volunteer to take responsibility
for the HP/UX port as I have no suitable machines. Said person should
be able to compile Icarus Verilog, manage HP/UX specific portability
issues, and be able to make precompiled packages when the stable release
is out.
I'm still looking for a similar volunteer for FreeBSD/{alpha,i386}.
Some more progress was made on support for PALs. I'm close to choosing
macrocell modes and configuring fuses. Won't be long now, folks.
Icarus Verilog snapshot 20001129
--------------------------------
few more constant propagation improvements this time, most notably
XOR an XNOR are now fairly complete. These are interesting as they are
generated by comparison operators so show up pretty often. And it is
common to compare numbers to constants. Thus, there are lots of oppor-
tunities for gate elimination!
Synthesis of unary ! now works. Unary ~| (reduction nor) should also
be in good shape now, as should binary || (logical or). Synthesis of
binary && is still a little shaky. Go ahead and file reports if you
trip on it. Binary != was broken with XNF synthesis, so that is also
fixed, along with a few cases of mangled XNF output. And there were
also a few bugs related to the CE of inferred DFFs, that didn't get
connected.
A *big* problem with synthesis occurred with non-blocking assignment.
Icarus Verilog simply failed to synthesize the r-value of the assignment
and all kinds of bad things happened. I fixed this, it's better now.
Whew! Lots of XNF synthesis bugs fixed! This is what happens when users
take the time to submit good bug reports.
There are also some bugs related to dead signal elimination that causes
Icarus Verilog to crash in some synthesis cases. These have been fixed
up so far as I know.
I have slightly improved root module detection of iverilog. If there is
only one module in a source file, it is pretty obvious that it is the root
module, even if it has ports. This is a common case for XNF synthesis
(especially when making small macros with Icarus Verilog) and should save
some typing and confusion.
-all previous netbsd patches have been incorporated (Thanks Steve!)
-changes from the authors announcement:
I fixed a problem with some systems not having getopt.h. I forget
which system it was, but configure takes care of it. I've also fixed
some broken install targets in the Makefiles.
I've added a new pin_count statement to PA files, so that the library
can provide to the user more information about the pinout of the device
in question. Applications may use this to help manage its pin binding
tasks.
A contributed 16l8 part description file was contributed, and included
in this release.
* A new part: wire jumper.
* Drag'n'drop from the part preview to place parts.
* A crude form of auto numbering when placing parts.
* Cleaned up makefiles and put some samples in
*<prefix>/share/oregano/samples/.
* Changed default spice executable name to spice3.
* Connection dots.
* A simple voltmeter function.
* Fix various ref/unref/sink design flaws, to
increased stability.
* Part browser remembers the previously selected part
when switching libraries.
* Should really work with libxml 2.x this time... :-)
* Reorganization of installation directories for model
and library files.
* The plot widget now features axis values.
* New parts: uA741 opamp and a simple zener diode.
* Parts and wires can be flipped horizontally and vertically.
* Enabled loading of simulation settings again.
* Added a simple text label item to put text on the sheet.
* Fixed the 'sometimes non-disappearing floating item' bug.
* Should now also work with libxml 2.x (untested).
* Switched C and B on the BJT transistor models.
* Removed the unfinished printing support for now.
* Redesign of lots of internals.
* Added lots of functionality to the parts library,
such as model files, and conditional values in templates.
* Improved a few of the icons.
* Fixed a bug where the name of the markers could not be edited.
* You can inspect the connection span, by holding Control while
moving the cursor over wires.
* Added the ability to rotate parts while placing them; press 'r'
to achieve this.
* Logging of Spice warnings and errors during simulation.
The messages can be shown in a log window.
* Beautification of the part browser UI.
* Added more tooltips and updated some translations.
* Fixed a few non-critical bugs.
* New and improved part properties editor.
* Improved user interface for the plot window.
* Internationalization fixes to netlist generation
and schematic loading/saving.
* The simulation now uses the user supplied time step size.
* French translation from David Monniaux.
* Even more refinement of the default library symbols/parts.
* Mission 'Code Cleaning' continues.
* Cut/copy/paste is implemented.
* The symbols are redrawn to look much nicer and more standard.
* Some new symbols, e.g. MOSFETs.
* There can be more than one part library, thanks to Elker Cavina.
* A bug with simulation time settings was fixed.
* There is a problem with some spice packages, that make them generate
binary output, even though the default should be ascii. This is now
fixed by telling spice to always output text.
* The help files are now installed in the rpm package.
* Lots of code restructuring and cleaning.
