Commit graph

5 commits

Author SHA1 Message Date
nia
5279ab7fb2 cad: Replace RMD160 checksums with BLAKE2s checksums
All checksums have been double-checked against existing RMD160 and
SHA512 hashes
2021-10-26 10:04:09 +00:00
nia
cf16b09db1 cad: Remove SHA1 hashes for distfiles 2021-10-07 13:20:26 +00:00
rillig
4f4f64fdce mark packages that fail with -Werror=char-subscripts
These packages are susceptible to bugs when confronted with non-ASCII
characters.

See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94182.

It takes some time to analyze and fix these individually, therefore they
are only marked as "needs work".
2020-05-20 06:09:03 +00:00
joerg
206a2f200a Not really C++11 ready. Don't define bool/true/false for C++. 2020-03-18 17:45:25 +00:00
kamil
c7561c1291 Import veriwell-2.8.7 as cad/veriwell
VeriWell is a full Verilog simulator. It supports nearly all of the
IEEE1364-1995 standard, as well as PLI 1.0.

Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in
the mid-1990 and was included with the Thomas and Moorby book.
2016-10-09 13:14:06 +00:00