Use BUILDLINK_INCDIR, BUILDLINK_LIBDIR for locations of linked headers
and libraries. Create a variable BUILDLINK_TARGETS whose value is the
list of build-link targets to execute.
(2) Use devel/readline/Makefile.readline to get readline support, and note
why GNU readline is required.
(3) Make this package work with xpkgwedge...the app-defaults file was
always being installed under ${X11BASE}.
many changes since the last snapshot. Mostly they involve expanded
VVP support. The VVP target now passes >200 of the tests from the
test suite. While not as complete as the VVM target, VVP is getting
closer and its _much_ _much_ faster.
increase in version number. From the XCircuit homepage:
Note that the March 28, 2001 version corrects a bug due to
dubious C syntax causing segmentation violations when xcircuit
was compiled without the debug option.
C Trivia question:
What does "x[a] = x[--a]" do?
Answer A: "x[a] = x[a - 1]; a--"
Answer B: "a--; x[a] = x[a]"
Answer C: either A or B, depending on your OS, compiler version,
and/or debug or optimizer switch.
Changes since the last packaged snapshot from the authors announcements:
Icarus Verilog snapshot 20010422
--------------------------------
I've integrated a bunch of UDP patches from Stephan Boettcher. These
go to the core of ivl, so if you use Icarus Verilog with UDPs, you
might want to give this a test for us.
Stephan has also added some ivl_target support for UDP devices. This is a
prerequisite to vvp support for UDP devices.
Some of you have been beating me over the head about disable, so the
vvp target now supports disable. It only works in certain very constrained
situations, but the idea is there and the more common cases are simply a
matter of getting around to them. I actually could use more examples of
the use of disable for the test suite.
In the process, I have settled on the interaction of threads and scopes,
and changed the %fork syntax to match. See the README.txt and opcodes.txt
file for details. The implementation of %end and %join simplified in
the process.
The vvp-tgt code generator supports a few more gate types. New gate
types are pretty easy to add, it's just boring grunt work. That's why
they've been popping up slowly.
I've also got certain behavioral shifts working. Only constant shifts,
so far, but this covers a pretty large percentage of the real world
uses of shift, I think.
I fixed a few specify block parse problems, so it should ignore
even more complex specify blocks now:-) One of these days I really will
properly support specify blocks.
PROGRESS
I was hoping to get vvp up to a similar level as vvm by the end of
April, but that doesn't look like it's going to happen. I'm up to 182
tests passed, compared to 318 of Icarus Verilog/vvm, so I have a ways
to go yet. I see no real point to making a release until I get up to
300 or so tests passed. That is the goal for 0.5 release.
But of course if vvp is enough for you, then it is soooo much faster
then vvm.
Icarus Verilog 20010415 Snapshot
--------------------------------
As with all the most recent snapshots, this is almost entirely progress
with the vvp code generator and simulation engine. I'm up to 159 tests
passed in the test suite, so I'm getting there. But there's still plenty
to go.
I also fixed what appeared to be a minor problem with elaboration of ?:
expressions in continuous assignments. The code was actually fine, it
was a spurious assert. This fix affects vvm as well.
Icarus Verilog/vvp now support <= statemements with internal delays.
That is, "foo <= #10 bar;" should work properly, and there are tests
in the suite that prove it. This is a pretty common syntax, so this
should help a lot of folks.
I also fixed a bug in the code generator that would cause it to put a
constant bit as a destination for the bitwise boolean operators. This
caused run-time asserts.
The event or support in vvp has been extended to now support arbitrary
width, so now you can for example wit for any changes in a 32bit reg.
This handles most of the likely cases, so @ statements should now be
pretty generally functional.
The handling of run-time threads has been revamped in preparation for
support of the disable statement. It also plugs a memory leak where
fork/join and task/function calls are invoked. And this version should
also clean up all those tiny initial foo=bar threads that all programs
seem to have. Threads that are done are now freed, along with their
memory, hopefully reducing the runtime memory footprint.
That's pretty much it this time 'round. Working with threads took some
time, so the progress isn't as flashy as it sometimes is.
There is still lots to do with vvp before 0.5, but I would appreciate
any feedback you can offer. It's complete enough already that I'm able
to accept bug reports on it, even if it turns out to be a "not supported
yet" type of thing. At this point, I'd be curious to know what hangups
are preventing its regular use.
Surface Impedance Method for Interconnect Analysis.
SIMIAN is a two dimensional frequency dependent series
impedance extraction tool for inerconnects and transmission
lines using conductors of rectangular or circular cross section.
The use of the surface ribbon method (SRM) greatly enhances
the speed of computation relative to the volume filament
method (VFM).
* Control Panel
- The Control Panel now has a "Tree View" which provides an
overview over all areas of EAGLE, like Libraries, User Language
Programs, Projects etc. The Control Panel's tree view supports
"Drag&Drop" to copy or move files and directories.
- Objects in the tree view have a context menu that can be
accessed by pressing the right mouse button.
- The menu option "Save project as..." is no longer available.
- New projects can now be created via the context menu in the
"Projects" tree item, or by selecting "File/New/Project" from
the Control Panel.
- The path settings in "Options/Directories" can now use the special
names "$HOME" and "$EAGLEDIR" to access the user's home directory
or the EAGLE installation directory, respectively.
- The new "Auto backup" feature will automatically save any modified
drawing into a safety backup file after a certain time.
* New Project Structure
- The names of files that are under the current project directory
are no longer written as absolute paths into the 'eagle.epf' file,
but rather relative to the project directory. This allows for
complete project directories to be easily copied or renamed.
- A project is now held in a subdirectory that contains a file
named 'eagle.epf' (which stores the location and settings of open
windows).
* User Interface
- The textual command menu can now be configured to display
aliased command buttons as well as submenus (see HELP MENU for
details).
- Changes made in the "Options/User interface" dialog now take effect
immediately for open editor windows.
- The cursor inside a layout or schematic editor window can now be
set to a "large" crosshair cursor (see "Options/User interface").
- The "Delete" icon was changed from a pencil with an eraser to
an 'X'.
- The "Split" icon was changed to better indicate what will happen.
* Keyboard and mouse control
- Alt-0 no longer popups up the window list, but leads directly to
the Control Panel.
- Pressing the Ctrl key while moving the mouse now scrolls the draw
window in any direction.
- The mouse wheel now zooms in and out in editor windows (zoom
factor can be adjusted in "Options/User interface/Mouse wheel
zoom", a value of '0' disables this feature and the sign of this
factor defines the direction of the zoom operation).
* Screen display
- The default for "minimum visible text size" has been changed to 3.
- The display mode parameter FAST has been dropped.
- By default the zoom factor in editor windows is limited so that
the resulting virtual drawing area does not exceed the 16-bit
coordinate range. This is necessary to avoid problems with
graphics drivers that are not 32-bit proof. If the graphics
driver on a particular system can handle coordinates that
exceeed the 16-bit range, "Options/User interface/Limit zoom
factor" can be switched off allow larger zoom factors.
* Design Rules
- EAGLE now supports a full set of Design Rules that are stored
inside the board file (and can also be saved to disk files).
Both the Design Rule Check and the Autorouter will use the
same set of rules.
- Newly created boards take their design rules from the file
'default.dru', which is searched for in the first directory
listed in the "Options/Directories/Design rules" path.
- Cream mask values are now measured "inwards" and thus have a
positive sign.
- The parameters AnnulusConduct and ThermalConduct are no longer
available. There are now checkboxes in the Design Rules dialog's
"Supply" tab that define whether a Thermal or Annulus symbol
shall have a "Restring" or not.
* Net Classes
- Nets and Signals now have a new parameter called "Net Class".
* Polygons
- When calculating polygons, the minimum distances defined in
the design rules and net classes will be taken into account.
* Design Rule Check
- The DRC now runs a lot faster.
- Progress is now displayed in a progress bar.
- Polygons from different signals with the same 'rank' are checked
against each other.
- The 'overlap' and 'minimum distance' check are no longer separate
checks.
- The DRC no longer checks an individual signal against everything
else. The newly introduced "Net Classes" can be used to do this.
- The rectangle for a selective DRC can now be defined with
"click&drag" (just as in the WINDOW command).
- Holes are no longer checked in the "Grid" check (only pads, vias,
smds and wires in signal layers are checked).
- Any objects in signal layers within a package are now checked
against each other.
* Long strings
- All names, values and texts can now be of any length.
- The User Language constants regarding name lengths still exist,
but the program uses these constants only for formatted output as
in the EXPORT command. They are still present for compatibility
only.
- There is no more limit to the number of members in a bus (bus
index values are limited to 0..511).
- Bus member names can now contain any characters, except
':', ',', '[', ']' and blanks.
* Wire styles
- Wires now have a new parameter 'Style', which can be set to one
of the following values:
Continuous _______________ (default)
LongDash ___ ___ ___ ___
ShortDash _ _ _ _ _ _ _ _
DashDot ___ . ___ . ___
- The variable for setting the bend type of a wire has been renamed
from Wires_Style to Wire_Bend to avoid confusing the two
parameters.
* Text fonts
- Texts can now have three different fonts: 'Vector' the program's
internal vector font (as used in previous versions)
'Proportional' a proportional pixel font (usually 'Helvetica')
'Fixed' a monospaced pixel font (usually 'Courier')
- When updating drawings from older versions, all texts are
converted to 'Proportional' font, except for those in layers
Top...Bottom, tRestrict and bRestrict, since these texts probably
need to be subtracted from signal polygons, which only works with
the 'Vector' font.
- The program makes great efforts to output texts with fonts other
than 'Vector' as good as possible. However, since the actual font
is drawn by the system's graphics interface, 'Proportional' and
'Fixed' fonts may be output with different sizes and/or lengths.
* Pads and Vias
- The diameter of pads and vias is now derived from the drill
diameter using the Design Rules (the pad and via diameter '0' is
now allowed and results in a diameter that is derived from the
current design rules). If a pad is defined with a diameter that
exceeds the one that would result from the current design rules,
the larger diameter is taken. The default value for the diameter
of newly created pads and vias is now '0' to allow the Design
Rules to define the actual diameters.
- Pads can have different shapes on Top and Bottom (they will always
be 'round' on the inner layers).
- The via shape now only applies to the outer layers (they will
always be 'round' on the inner layers).
- The diameter of pads with shape X/YLongOct now defines the
smaller side of the pad (formerly the wider side). Existing
files will be modified accordingly during the update.
- By default vias no longer generate Thermal symbols in supply
layers.
* Round SMDs
- SMDs have a new parameter "Roundness", which can range between
0 and 100 and defines the percentage by which the corners are
"rounded". A value of 0 (default) results in a rectangle, while
a value of 100 results in a circular shape (if the x and y
dimension of the SMD are the same), which can be used for BGAs.
- The SMD command accepts roundness values as numbers with a
leading '-' (to be able to distinguish it from the SMD size
values). The CHANGE command has a new option "Roundness".
* New Library structure
- What was called a "Device" in previous versions is now
called a "Device Set". A "Device Set" consists of the gate
definitions and several actual devices, implemented through
"Package Variants"
- The PACKAGE command can now assign several different package
variants to a device (as in 7400N, 7400D,...).
- The new command TECHNOLOGY can be used to define various
"technology" variants for a device's package variants (as in
74LS00N, 74S00N,...).
- The CHANGE command has the new options PACKAGE and TECHNOLOGY,
which can be used to select from the packages and/or technologies
a device set defines. This can be done from within the schematic
or board.
- The new command DESCRIPTION can be used to provide detailed
textual information about a device, package or library.
- The CONNECT dialog now allows copying pin/pad connections from
an other package variant. Only those package variants are offered
in the "Copy from" combo box that have the same pad names as the
current package variant (only connected pads are checked).
- The CONNECT dialog now asks the user if he want's to discard
any changes before cancelling the dialog.
- The CONNECT command can now handle gate names that contain
periods.
- The device editor now displays a list of package variants, a
preview of the current package and the description of the
device.
* Automatic Library update
- If a library has been modified after parts or packages from it
have been added to a schematic or board, the new command UPDATE
can be used to automatically update all used library objects with
their latest version (see "Help Update").
- The UPDATE command can be selected from the "Library" pulldown
menu in a board or schematic, or from the context menu of a
library in the Control Panel. It is also possible to drag&drop
a library from the Control Panel onto a schematic or board
drawing and perform the update that way.
* Bill Of Material
- The User Language Program 'bom.ulp' to generate the "Bill Of
Material" has been rewritten. It now has a dialog in which the
user can interactively generate the BOM, pulling in additional
data from a user defined database file. Use "RUN bom.ulp" and
click on the "Help" button for more information.
* Generating Outlines for milling prototypes
- The User Language Program 'outlines.ulp' can be used to generate
the data necessary to control a milling machine for generating
a prototype board.
* User Language
- The User Language now supports user defined dialogs as well as
standard file dialogs and message boxes.
- The RUN command now accepts additional arguments that are
available to the ULP as 'argc' and 'argv' parameters.
- Data can now be read into a ULP.
- The new lookup() function can be used to perform database
lookups.
- The new fileglob() function can be used to do a directory
search.
- The new fileerror() function can be used check for I/O errors.
- The 'exit()' function can now have a string parameter which is
sent to the editor window and executed as a command string.
- ULPs can now include other ULP files with the new #include
directive.
* Script files
- Script files can now call other scripts (as long as no
recursive call is made).
- Script files can now contain comments. Everything after
(and uncluding) a '#' character will be ignored.
- The 'eagle.scr' file is now first searched for in the current
project directory (which is equal to the current working
directory in case there is no project open) and then in the
directories listed in the Control Panel's
"Options/Directories/Scripts".
* Autorouter
- The Autorouter can now route "through" signal polygons (this
can be controlled by the new cost factor 'cfPolygon').
- The Autorouter control parameters are now stored inside the
board file. They can be saved to and loaded from external files
via the Autorouter dialog. Existing control files will be
automatically read and stored in the board file when updating
files from previous versions.
- The Autorouter and DRC now use the same set of Design Rules.
- When saving Autorouter control parameters to disk, the minimum
distance parameters are no longer part of that file.
- There can now be any number of 'Optimize' passes. By default
there are now 4 'Optimize' passes.
- Each pass can be separately activated or deactivated.
- The Autorouter can now route different wire widths and minimum
distances simultaneously by using "Net Classes".
- The minimum routing grid is now 0.02mm (about 0.8mil).
- The default control parameters and the internal handling of
cfChangeDir have been modified to avoid jagged tracks.
* ADD command
- The ADD command can now be used with wildcards ('*' or '?') to
find a specific device. The ADD dialog offers a tree view of
the matching devices, as well as a preview of the device and
package variant.
- To add directly form a specific library, the command syntax
ADD devicename@libraryname
can be used. 'devicename' may contain wildcards and
'libraryname' can be either a plain library name (like "ttl"
or "ttl.lbr") or a full file name (like
"/home/mydir/myproject/ttl.lbr" or "../lbr/ttl").
- If a device or package shall be added, and there is already
such an object (with the same name from the same library) in the
drawing, an automatic library update will be performed which
replaces the existing object in the drawing with the current
version from the library.
- The new command UPDATE can be used to update all parts in a board
or schematic with modified library versions (see "Help Update").
* CHANGE command
- CHANGE LAYER for wires and polygons now works between any
layers within packages and symbols.
* CONNECT command
- Pressing the SPACE key in the CONNECT dialog while a list element
has the focus will now perform the 'connect' or 'disconnect'
action, respectively.
* DELETE command
- If the last supply symbol of a given type is deleted from a net
segment that has the same name as the deleted supply pin, that
segment is now given a newly generated name (if there are no other
supply symbols still attached to that segment) or the name of one
of the remaining supply symbols.
* DISPLAY command
- The new parameters '?' and '??' can be used to control what
happens if a layer that is given in a DISPLAY command does not
exist in the current drawing. See "Help Display" for details.
* GROUP command
- If the selected group is empty, the GROUP command no longer
displays a message box saying "Group is empty". It rather prompts
that message in the status bar (with a beep) and stays active for
a new group definition.
* ERC command
- The ERC now lists the package names when reporting parts/
elements with inconsistent packages.
- The ERC now detects inconsistencies between the implicit power
and supply pins in the schematic and the actual signal
connections in the board.
- The ERC now checks for missing junctions and overlapping wires
and pins.
* ERRORS command
- The ERRORS dialog is no longer modal (it stays "on top" of the
editor window) and can be kept open while resuming normal
editing in the editor window. The various error types are now
listed more detailed.
* EXPORT command
- The EXPORT can now export image files (BMP, PNG, etc.). See
"Help/EXPORT" for details.
* NET and BUS command
- If a net wire is placed at a point where there is already
another net or bus wire or a pin, the current net wire will be
ended at that point (in previous versions the user had to click
twice to end a net wire).
* PASTE command
- When pasting objects into a drawing that already contains earlier
(different) versions of these objects, an automatic library
update will be performed which replaces the existing objects in
the drawing with the new versions from the paste buffer.
* PRINT command
- The PRINT dialog's "Page setup" now allows border values that
are smaller than the initial values derived from the printer
driver. To get back to the original default you can enter '0'.
* REMOVE command
- The REMOVE command can now handle device, symbol and package
names with extension (for example REMOVE name.pac).
* RENAME command
- The RENAME command now allows '.' in names.
- The RENAME command can now handle device, symbol and package
names with extension (for example RENAME name1.pac name2[.pac]
- note that the extension is optional in the second parameter).
* REPLACE command
- The REPLACE command can no longer be used with active forward-
and backannotation. This is due to the now complete definition
of a device set with all its package variants. Use the CHANGE
PACKAGE command to select one of the defined package variants,
or use the UPDATE command to update a package with a modified
version from the same library.
* SET command
- The SET options for Thermal and Annulus parameters as well as
the Solder Stop and Cream mask data have been removed.
- The SET variables DRC_SHOW and DRC_COLOR are now obsolete
(progress in the Design Rule Check is now displayed in a
progress bar).
- The SET variable MAX_ERROR_ZOOM is now obsolete. The ERRORS
dialog is no longer modal (it stays "on top" of the editor
window) and zooming can be done with the usual WINDOW commands
or buttons.
* SHOW command
- Highlighted objects are now kept highlighted during subsequent
window operations.
- Pressing ESCape in the SHOW command now lowlights the currently
highlighted object.
* USE command
- The USE command is now mainly for use in script files.
* CAM Processor
- The CAM Processor no longer supports matrix printers. Use the
PRINT command to print to the system printer.
- The CAM Processor no longer prints sheets. Use the PRINT
command instead.
* Parameter storage
- User specific parameters are now stored in an "eaglerc" file.
At program start, parameters are read (in the given sequence)
from the files
prgdir/eaglerc
/etc/eaglerc
$HOME/.eaglerc
where prgdir means the directory that contains the EAGLE program
file.
* Command line options
- The options '-A' and '-T' are now obsolete (thermal and annulus
data is now defined in the Design Rules).
- The options '-B' and '-M' are now obsolete (solder stop and
cream mask data is now defined in the Design Rules).
- The option '-C' is now obsolete, since the CAM Processor no
longer supports matrix printers (all printing is done with the
PRINT command).
- The options '-Z' and '-Y' are now obsolete (drill symbols are
configured in "Options/Set/Drill" and are stored in the user
specific "eaglerc" file).
* Miscellaneous
- The DOS and OS/2 platforms are no longer supported.
- Due to changes in the file data structure you will most likely
be asked whether to run the ERC when loading a board/schematic
pair created with an earlier version of EAGLE.
- Files from earlier versions of EAGLE may contain library objects
with the same names. This was caused by PASTE or ADD operations
with modified devices or packages. Version 4 no longer allows
this to happen, and therefore needs to make sure updated files
do not contain multiple objects with the same name. In order to
assure this, the update routine adds the '@' character and a
number to the names of such library objects.
- The library editor can now edit devices and symbols, even if the
user's license does not contain the schematic module.
- Avoiding multiple 'Save?' prompts for boards and schematics that
are connected via f/b annotation.
- When a file is modified while updating from a previous version
the resulting update report is now presented in a separate text
window.
Microstrip Patch Antenna Calculator. MPAC analyzes various parameters
including impedance and resonant frequency for a rectangular microstrip
patch antenna.
changes since last snapshot are (from the authors email)
verilog-20010407
--------------------
Still more progress on the new VVP simulation engine:
As with last week, this snapshot includes a lot of work on the ivl_target
API in support of code generation for vvp. Also, the vvp execution engine
has progressed some.
In fact, vvp has grown up to understand signed vectors and some signed
expressions. The signed vectors are mostly for VPI use, the signed
comparison instructions actually do signed work. Case comparisons are
new, along with %and and %or instructions, and %nor/r for reduction.
I also added a few new gate types to the .functor support.
A bug in the propagation of values by %set instructions has been fixed.
Specifically, the %set instruction not only sets the value of the .var
that it references, but also executes the propagation events that result.
This fixed some event ordering bugs.
Some VPI support needed by system.vpi is added to vvp to allow it to
properly handle signed signals, decimal values, and a few other details.
$display should work much better then it did last week.
Back in the vvp.tgt code generator, lots of new stuff is happening.
Several of the bitwise binary operators have been added, as well as
more comparison operators. This includes handling of signed expressions.
This also implies that vvp.tgt generates the proper .net vs .net/s
and .var vs .var/s statements.
User defined functions and tasks are now working. In fact, the vvp
target probably handles more functions (in behavioral code) then the
vvm engine. I've received several bug reports about user defined functions
with loops, that don't work under vvm. These should work with vvp.
Non-blocking assignments now work, too.
All forms of case/casex/casez are supported by the code generator, and
use the proper compare instructions. Forever, Repeat and While loops
also work now. A few bugs in event handling, and all the edge types
(including behavioral triggers) should work with limitations. Event or
is still in the works, and any-edge of large vectors (>4 bits) does not
work.
*Whew!*
As you can see, a *lot* of stuff is happening. I'm up to passing 110+
tests in the regression test suite (Icarus Verilog/vvm passes 318 tests)
so the changes are actually making things work. Test and be merry!
verilog-20010331
--------------------
More and more progress on VVP. More and more snapshots.
A lot of work has been done to the ivl_target loadable target API.
This API is growing to support the also growing tgt-vvp target. I've
added support for case statements, event triggers fork blocks.
Of course this also means that the tgt-vvp code generator and the
vvp simulator now support constructs including case, events, and
parallel blocks.
I've also fixed up the driver to properly report errors that tgt-vvp
detect. This makes the test suite regression script work a lot better.
I'm up to more then 70 tests in the test suite passing. I'm finding
that writing the code generator for vvp assembly is a *lot* easier
then writing a code generator for C++/vvm. Fortunately, the vvp
assembler is pretty fast.
At any rate, the vvp simulation engine is starting to show signs of
being useful. It still does not cover nearly as much of Verilog as
vvm, but what it does cover is so much faster that it may be worth
your while to try it out. And more eyes looking at it can only be a
good thing.
the authors announcement are:
There are a few bugs in the main compiler that are fixed. There has
also been an extension to the $fopen that adds support for opening
files for reading. The $fgetc has been added to take advantage of this.
This was done on the VPI side, although a slight extension to the mcd
functions was created.
The real news is the vvp simulation engine. I've added the tgt-vvp
code generator source and the vvp assembler/simulator, and the combination
actually produces the occasional working program. And it makes them
very quickly. So far as I can tell now, I am going to be very pleased
with the final outcome when this work is complete. However, it is not
at all ready to use. This snapshot is mostly to give a preview of things
to come to a wider audience.
HOW VVP WORKS
If you are accustomed to the existing vvm behavior, you remember that
the vvm simulator works by generating C++ and feeding that to the g++
compiler. Many of you are painfully aware of that.
VVP does *not* work like that. Instead of generating C++, the
generator emits assembly language for an abstract simulator processor.
The processor that the assembly targets doesn't really exist, but the
vvp program, included in this Icarus Verilog snapshot, assembles the
code to data structures in memory, then efficiently emulates the abstract
processor.
So the simulation of a program via vvp works by first compiling the
Verilog to vvp assembly. The vvp.tgt modules generates the code, and
is envoked when you use the ``-tvvp'' switch to iverilog.
The vvp assembly file so created is then passed to the vvp program to
be assembled and executed. There is a single vvp input file that is the
design to simulate. The vvp assembler is designed to execute the design
efficiently.
HOW TO LEARN MORE
The ivl_target.h header file describes the loadable target API that
the vvp code generator uses to gain access to the design. Then the
tgt-vvp directory contains the implementation of the vvp code generator.
The vvp directory contains the implementation of the assembler/simulator
that runs the compiled design. The README.txt file describes how the
vvp program works in general, and points to other txt files. There are
a variety of other .txt files in the vvp directory that describe how
the major components of the vvp program work.
first component is now a package name+version/pattern, no more
executable/patchname/whatnot.
While there, introduce BUILD_USES_MSGFMT as shorthand to pull in
devel/gettext unless /usr/bin/msgfmt exists (i.e. on post-1.5 -current).
Patch by Alistair Crooks <agc@netbsd.org>
QCad is a simple 2D CAD System. With QCad you can easily construct and
modify drawings with ISO-texts, dimensions, hatches and many other
features and save them as DXF-files. These DXF-files are the interface
to many CAD-systems such as AutoCAD and many others.
While here, update MASTER_SITE.
changes from last packaged version:
* Changes in Dinotrace 9.1b 2/13/2001
**** Documentation updates.
* Changes in Dinotrace 9.1a 1/22/2001
** Added analog waveform format. [Dave Colson]
Includes new Signal Waveform menu and signal_waveform command.
* Changes in Dinotrace 9.0m 11/21/2000
**** Fixed a bug reading compressed tempest on Digital UNIX. [Steve Hoover]
up a possibly out of date installed header from ${LOCALBASE}/include.
Note that while we don't support installing a pkg when a previous version
is installed, we should still be able to build it.
Problem noted in private email from Lennart Augustsson.
from the authors announcement:
So many things have changed since version 0.3 that there is no point
in listing them. There have been tons and tons of bug fixes and the
language coverage is better, and so on and so forth. It's just so very
much better then version 0.3:-)
speaking as a user, some of my personal favorites are:
- support for signed variables
- iverilog now gives correct return codes (which makes 'make' much happier)
for a more complete list, the commit messages for
pkgsrc/cad/verilog-current/Makefile contain the changes for each
development snapshot between verilog-0.3 and verilog-0.4
considered stable. Xcircuit now has the ability to pass parameters
to objects. For the moment, this only works with string parameters.
Integral parameters will be added in upcoming versions.
bug fixes and signed support (yay!).
detailed changes since last packaged snapshot from the
authors announcements:
Icarus Verilog snapshot 20010113
--------------------------------
We're getting close to release candidates. Maybe another snapshot, then
I start with making 0.4 release candidates. So lets get this tested so
that I can move forward!
This snapshot largely fixes a whole bunch of bugs. I'm working feverishly
to catch up to the reported bugs, but they are coming in about as fast
as I can resolve them. (Not that I'm complaining, mind you. These PRs
are really helping me make it better.) But that means I'm going to just
concentrate on getting as many PRs done as I can before the release.
The syntax of functions and tasks has been expanded to allow parameters.
This is not a common thing to do, but someone puts parameters if functions
The syntax of functions and tasks has been expanded to allow parameters.
This is not a common thing to do, but someone puts parameters if functions
so I had a PR to fix:-) Also I caught a problem with executing functions
that take no input parameters. In fact, a bunch of function related bugs
were fixed. I lost track of em all.
Ports of tasks weren't elaborated properly. I fixed this and a few related
problems so most legal l-values should work as task port expressions now.
Memories within tasks should also work properly now.
Speaking of ports, I now report errors when there is a port direction
for module ports that don't exist. In fact, there are a whole bunch of
cases where I've added required error messages.
The %d format of display strings now displays signed negative values as
negative values instead of the unsigned equivalent. This goes along with
the other signed arithmetic features from the -2000 standard that are now
supported.
I fixed up the Makefiles (thanks to a contribution) to support build using
the VPATH capabilities of the makefile. You should be able to compile for
multiple targets now from a shared source directory.
Icarus Verilog snapshot 20010106
--------------------------------
I'm just managing to barely keep up with the bug reports arriving in
the bug tracking system. I'm pleased with the success of the ivl-bugs
robot. These bug reports have allowed me to better manage and record
progress. Keep those bug reports coming!
I've added support for arrays of integer and time variables, as well
as the Verilog 2000 initialization syntax for these types. I have also
made some internal changes to integer support. Integers are now just
a shorthand for ``reg signed [31:0]'' and signed variable support has
made some internal changes to integer support. Integers are now just
a shorthand for ``reg signed [31:0]'' and signed variable support has
been generalized. This makes it easier on the code generators, as they
do not need to know that a variable was a integer, a time, a foo or a bar.
I few constant propagation errors have been fixed. Continuous assignments
of constants to nets should behave correctly now.
Many people noticed lack of expression support for parameters. In fact,
the problem was a lack of support for a bunch of specific operators. I've
added many operators. This has the side effect of improving constant
propagation as well, in some cases finding more dead code to eliminate.
This also affected expressions that were index expressions of memories
and vector declarations.
The / operator in continuous assignment expressions is fixed. There were
a few size related issue here that are now fixed.
I've added to the i3331364-notes.txt file a clarification of my position
on parse of repeat statements. This position is compatible with XL behavior.
Passing parameters to user defined functions in behavioral code was pretty
darn broken. I managed to fix this. You can tell that not many people use
user defined functions:-) (It doesn't help that Icarus Verilog is picky
about them.)
For vvm, I've put some effort into optimizing the compile time of programs
by reducing the size of the output code. I've reduced redundancies some,
and used loops to handle vectors where possible.
A few bugs related to $dumpvars were cleaned up. Function scopes work.
out of date - it was based on a.out OBJECT_FMT, and added entries in the
generated PLISTs to reflect the symlinks that ELF packages uses. It also
tried to be clever, and removed and recreated any symbolic links that were
created, which has resulted in some fun, especially with packages which
use dlopen(3) to load modules. Some recent changes to our ld.so to bring
it more into line with other Operating Systems also exposed some cracks.
+ Modify bsd.pkg.mk and its shared object handling, so that PLISTs now contain
the ELF symlinks.
+ Don't mess about with file system entries when handling shared objects in
bsd.pkg.mk, since it's likely that libtool and the BSD *.mk processing will
have got it right, and have a much better idea than we do.
+ Modify PLISTs to contain "ELF symlinks"
+ On a.out platforms, delete any "ELF symlinks" from the generated PLISTs
+ On ELF platforms, no extra processing needs to be done in bsd.pkg.mk
+ Modify print-PLIST target in bsd.pkg.mk to add dummy symlink entries on
a.out platforms
+ Update the documentation in Packages.txt
With many thanks to Thomas Klausner for keeping me honest with this.
Changes since the last packaged snapshot are (from the authors announcements):
Icarus Verilog snapshot 20001216
--------------------------------
This is the last snapshot before the holidays, so I hope it has your
favorite present in it. A lot of PR#s have been dealt with, and for a
brief moment I felt like I was getting ahead of the pending list:-)
I've added support for non-integer times, at least in a few contexts.
The `timescale directives should interact properly with the decimal
point in delays, causing more accurate timing simulations. This should
make vendor-supplied libraries work much better.
I've added support for signed reg variables. Signed expressions should
now generally do the right thing, but this feature needs much more testing,
and many more tests in the test suite. However, I do know that signed
comparisons should work properly. Bug reports for problems with signed
arithmetic are encouraged.
Many people have been having troubles with Cygwin compilation. The
problem was with the latest version of binutils. Venkat came up with a
solution that works with old and new binutils, so you can now compile
with the very latest cygwin software. This should make things a lot
easier for a lot of people.
I've made initial steps toward an HP/UX port. The configure script should
detect the right dl library to use, and the t-dll target should be able
to load loadable targets. I am looking for a volunteer to take responsibility
for the HP/UX port as I have no suitable machines. Said person should
be able to compile Icarus Verilog, manage HP/UX specific portability
issues, and be able to make precompiled packages when the stable release
is out.
I'm still looking for a similar volunteer for FreeBSD/{alpha,i386}.
Some more progress was made on support for PALs. I'm close to choosing
macrocell modes and configuring fuses. Won't be long now, folks.
Icarus Verilog snapshot 20001129
--------------------------------
few more constant propagation improvements this time, most notably
XOR an XNOR are now fairly complete. These are interesting as they are
generated by comparison operators so show up pretty often. And it is
common to compare numbers to constants. Thus, there are lots of oppor-
tunities for gate elimination!
Synthesis of unary ! now works. Unary ~| (reduction nor) should also
be in good shape now, as should binary || (logical or). Synthesis of
binary && is still a little shaky. Go ahead and file reports if you
trip on it. Binary != was broken with XNF synthesis, so that is also
fixed, along with a few cases of mangled XNF output. And there were
also a few bugs related to the CE of inferred DFFs, that didn't get
connected.
A *big* problem with synthesis occurred with non-blocking assignment.
Icarus Verilog simply failed to synthesize the r-value of the assignment
and all kinds of bad things happened. I fixed this, it's better now.
Whew! Lots of XNF synthesis bugs fixed! This is what happens when users
take the time to submit good bug reports.
There are also some bugs related to dead signal elimination that causes
Icarus Verilog to crash in some synthesis cases. These have been fixed
up so far as I know.
I have slightly improved root module detection of iverilog. If there is
only one module in a source file, it is pretty obvious that it is the root
module, even if it has ports. This is a common case for XNF synthesis
(especially when making small macros with Icarus Verilog) and should save
some typing and confusion.
-all previous netbsd patches have been incorporated (Thanks Steve!)
-changes from the authors announcement:
I fixed a problem with some systems not having getopt.h. I forget
which system it was, but configure takes care of it. I've also fixed
some broken install targets in the Makefiles.
I've added a new pin_count statement to PA files, so that the library
can provide to the user more information about the pinout of the device
in question. Applications may use this to help manage its pin binding
tasks.
A contributed 16l8 part description file was contributed, and included
in this release.
* A new part: wire jumper.
* Drag'n'drop from the part preview to place parts.
* A crude form of auto numbering when placing parts.
* Cleaned up makefiles and put some samples in
*<prefix>/share/oregano/samples/.
* Changed default spice executable name to spice3.
* Connection dots.
* A simple voltmeter function.
* Fix various ref/unref/sink design flaws, to
increased stability.
* Part browser remembers the previously selected part
when switching libraries.
* Should really work with libxml 2.x this time... :-)
* Reorganization of installation directories for model
and library files.
* The plot widget now features axis values.
* New parts: uA741 opamp and a simple zener diode.
* Parts and wires can be flipped horizontally and vertically.
* Enabled loading of simulation settings again.
* Added a simple text label item to put text on the sheet.
* Fixed the 'sometimes non-disappearing floating item' bug.
* Should now also work with libxml 2.x (untested).
* Switched C and B on the BJT transistor models.
* Removed the unfinished printing support for now.
* Redesign of lots of internals.
* Added lots of functionality to the parts library,
such as model files, and conditional values in templates.
* Improved a few of the icons.
* Fixed a bug where the name of the markers could not be edited.
* You can inspect the connection span, by holding Control while
moving the cursor over wires.
* Added the ability to rotate parts while placing them; press 'r'
to achieve this.
* Logging of Spice warnings and errors during simulation.
The messages can be shown in a log window.
* Beautification of the part browser UI.
* Added more tooltips and updated some translations.
* Fixed a few non-critical bugs.
* New and improved part properties editor.
* Improved user interface for the plot window.
* Internationalization fixes to netlist generation
and schematic loading/saving.
* The simulation now uses the user supplied time step size.
* French translation from David Monniaux.
* Even more refinement of the default library symbols/parts.
* Mission 'Code Cleaning' continues.
* Cut/copy/paste is implemented.
* The symbols are redrawn to look much nicer and more standard.
* Some new symbols, e.g. MOSFETs.
* There can be more than one part library, thanks to Elker Cavina.
* A bug with simulation time settings was fixed.
* There is a problem with some spice packages, that make them generate
binary output, even though the default should be ascii. This is now
fixed by telling spice to always output text.
* The help files are now installed in the rpm package.
* Lots of code restructuring and cleaning.
changes since the last packaged version (from the authors announcements):
Icarus Verilog snapshot 20001119
--------------------------------
The big change here (code wise) is improved and corrected constant
propagation. I was missing OR, NOR, NAND and XOR propagations, and
got some of the AND calculations wrong. This fixes this shortcoming
and in some cases this actually may speed up your compile a tiny bit.
Some more dangling signals are also eliminated.
supply nets are now working (PR#17). They also will trigger constant
propagation (as they have constant values) in certain cases.
Those of you doing cygwin compiles have trouble compiling parse.cc. I've
put into the cygwin.txt some slightly better instructions for dealing with
this situation, when it comes up.
I've also added missing symbols to ivl.def, so that tgt-stub properly
links.
Icarus Verilog snapshot 20001112
--------------------------------
This snapshot includes support for MOS et al devices as contributed
by Tim Leight. It appears to actually work as advertised, and I also
have from him a collection of tests that I'll be adding to the test
suite as soon as I get copyright information from him. So if you have
been dreaming of simulating MOS devices with Icarus Verilog, give this
a try. This update also fixed PR#27.
I've also cleared up a few bugs related to unconnected module ports.
Module port syntax is pretty byzantine, as PR#38 shows.
The loadable target API has gained access to flip-flops. This is required
for PLD code generation to work. I think the ivl_target API now supports
the minimum devices needed to generate PLD files, and I'm on to the task
of getting ancillary PAL support working.
Icarus Verilog snapshot 20001104
--------------------------------
Yes, I've managed to find the right bits to get Icarus Verilog to compile
on RedHat 7.0, and this snapshot includes those fixes. It took some back-
and-forth with tech support at RedHat to get it going.
I've also fixed up make check so that it works in general. If you use
"make check" after building, the makefile will run the examples/hello.vl
program through the local parts to make sure they minimally work.
I've added support for the "time" data time and more complete support
for the $time system function. These should work properly in all cases
now, so cases of not working are worthy of a bug report.
I've also integrated a re-implementation of sequential UDPs from Stephan
Boettcher, so I would appreciate it if all you folks using primitives
give this a fresh test. (It should be an improvement.)
This is a relatively small message, which doesn't reflect the complexity
of the changes. The "time" support in particular caused a lot of threads
to be pulled. Also, I've been doing some PLD stuff on the side, so I've
been busy.
I've also knocked of PR#11, 14, 33, 34, 39 and a few other bugs.
changes (from the announcement):
The libipal library has gained access to more structural information
about the device, including enable SOPs. It is also now possible to
lookup a SOP by name and by pin. Also, access to sop fuse positions
has been improved.
The toplevel makefiles were changed to use $(MAKE) instead of make.
There are a few other niggling makefile fixes as well.
ipalrev and ipaledit now both take the -p flag allowing you to choose
the architecture for your device, and there are now two devices to
choose from. (both 22v10s:-)
ipalrev was seriously confused about inversions and the sense of things,
but that should be all cleared up now. It does a decent, if not complete,
job of decompiling 22v10 designs.
And finally, the PA file format has been extended to accommodate the
new library features, and PA files are now named according to a naming
convention for identifying devices.
from the NEWS file:
New in 20001123:
- Saving wave and panel configuration as guile scripts.
- Executing guile scripts from menu or command line (-s <script> option)
- Remote control using the gwave-exec and gwaverepl utilities
New in 20001004:
- Spice3/Ngspice rawfile improvements: binary files now work!
- Other minor file-reading improvements.
- spice source code to examples for which I could still find it.
New in 20001004:
- Major improvements to handling of binary files produced by HSPICE.
- Overhaul of input of spice3/ngspice raw files; more robust and tolerant
of complex numbers.
- User interface improvements: tooltips added. User's .gwaverc no longer
required to do lots of standard setup. system.gwaverc can be copied
to $HOME/.gwaverc and edited to taste.
- sp2sp utility included for converting any spice file readable by gwave into
a convenient tabular ascii format.
from the history file:
----------------------
New features:
1. New probes: diode G, mos IBD, IBS, GBD, GBS.
2. New options: "floor" and "vfloor". (Floor was in the manual, but
not in the simulator.)
Improvements, bug fixes, etc.
1. There is a change to the way behavioral modeling conditionals are
handled. It should now be 100% compatible with SPICE, considering the
subset that duplicates SPICE. There are still significant extensions
beyond SPICE, particularly that you can have behavioral resistors,
capacitors, inductors, etc.
2. Parameter default calculations are now done in a manner consistent
with Spice 3f5. Previously, it was supposedly consistent with Spice
2g6.
3. A bug in calculation of threshold voltage of the level 6 model, for
P channel devices, has been fixed.
4. A bug in calculation of Meyer capacitances when the device is
reversed has been fixed. This bug sometimes caused a discontinuity at
vds=0.
5. I have added some smoothing to the Meyer mos capacitor models.
This improves convergence. The down side is that sometimes the
answers are different. It is probably a little better, when
considering closeness to reality, but it is still Meyer's model.
6. MOSFET parasitic diodes are now the same as those used in Spice.
7. There are subtle changes in the diode model. I think this usually
improves convergence.
8. Charge calculation in Meyer capacitors and diode capacitiors is now
supposedly Spice 3 compatible.
9. An error in BSIM3 scaling has been fixed.
Some things that are still partially implemented:
1. Internal element: non-quasi-static poly-capacitor.
2. BSIM models, charge effects.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. The makefile does not set up the proper link for the model
compiler. You need to do it manually.
3. A bad setting of "vmax" and "vmin" can lead to convergence to a
nonsense result. It is not as bad now as it used to be.
note, this is the development snapshot version of the package. As stable
releases become available, there will be a ipal package.
from DESCR:
Icarus PAL is a set of libraries and utilities for manipulating PAL
designs. The design information is conveyed in the industry standard
JEDEC file format.
Icarus PAL accepts parts descriptions that detail the device
structure, capabilities and pinouts so that software can be written to
work relatively independent of the part type. These parts descriptions
also describe how the fuses of a device are arranged, so that
synthesis tools can generate fuse maps to get the desired
functionality and pinout. See as a commented example the description
in the pa/pal22v10.pa description.
The ipaledit program takes as input a .JED file and displays the PAL
design. It shows the sum-of-products as a fuse matrix, and shows the
macrocell configurations in convenient form.
The ipalrev program takes as input a .JED file and reverse compiles
it, producing a Verilog program that logically describes the
design. This use useful for moving old designs to new tools.
Please note that this package is a development snapshot and while it contains
the latest and greatest features, it may be buggy as well. When
available there will be a seperate ipal package which will be made of
the stable releases.
from DESCR:
The program is a viewer and editor for:
-GDSII files, KEY files (own made extended GDSII in ascii format) and
DAVID MANN files (flash format for mask plotting)
Features:
-It allows to draw primitives on a chosen layer, and to manipulate them.
-stack oriented tools allows zooming while drawing new primitives and
editing them. This also makes it possible to draw extremely accurate.
-primitives on the layers or/can be transparent colors and fill patterns
can be set on a layer basis
-drawing order of layers can be changed
-a hiearchy of pictures, named structures, can be handled and manipulated
-saving as a bitmap and other formats.
-measuring distances
-adding user defined properties to primitives
-boolean OR AND EXOR A-B B-A
-positive and negative process offset
-circle recognition in polygon and polyline data.
-move copy delete etc.
-transformations (scaling , rotation , moving)
-flatten the hiearchy of the drawing
-drivers for CNC (laser and milling machinery)
NG-SPICE is the program being developed as the replacement for Berkeley
SPICE. Using the Berkeley code as a starting point, the NG-SPICE team
is working on improving the build system, adding to the models, and
improving the analysis capability.
SPICE is a general-purpose circuit simulation program for nonlinear dc,
nonlinear transient, and linear ac analyses. Circuits may contain resistors,
capacitors, inductors, mutual inductors, independent voltage and current
sources, four types of dependent sources, lossless and lossy transmission
lines (two separate implementations), switches, uniform distributed RC
lines, and the five most common semiconductor devices: diodes, BJTs, JFETs,
MESFETs, and MOSFETs.
The program xcircuit is a generic drawing program tailored especially
for making publication-quality renderings of circuit diagrams (hence
the name). The output is pure PostScript, and the graphical interface
attempts to maintain as much consistency as possible between the X11
window rendering and the final printer output.
xcircuit is mouse, menu, and keyboard-driven, with the emphasis on
single-character keyboard macros.
Package provided by Jason Beegan <jasontd@indigo.ie> in PR 11383 with
some minor modifications by me.
from the authors announcement:
-----------------------------
The loadable target module API is starting to take shape.
That is the major thrust nowadays with Icarus Verilog, after all, so
progress is being made here. The biggest change is in fact a philosophy
change. The target module now needs only a single symbol -- target_design --
to receive the whole design. The target module can from there and using
the API access the entire design randomly. So if you wanted to implement
a graphical browser, you could:-)
I've added support for the l-values of procedural assignments, and also
back pointers to objects that reference ivl_nexus_t objects. This closes
the loop so that there should be no dead-ends in the design.
I've clarified and expanded the descriptions in the ivl_target.h header
file. There should be just about enough documentation to properly used
all the various types. (Have any of you tried to write GIMP plug-ins?
Have you looked at the libgimp header files? Have you seen any comments
there?-( I won't ever sink to that level, I hope.)
I've also imtegrated updates to the Cygwin32 port to support loadable
targets under Cygwin32. After much struggling, Venkat managed to discover
the secret magic needed to get load time symbol binding to work. Hopefully
I didn't break it too bad when I changed the API again. (I think it is
still fine.)
as files instead of requiring the user to install one of our largest packages
just to build them. Note, in the previous version of this pkg, the docs generated
with latex weren't even being installed (!).
Notable changes since the last pkged version are:
Gwave NEWS --- history of user-visible changes. -*- text -*-
New in 20000518:
- Logarithmic scales working on both X and Y axis.
New in 20000509:
- First public guile/guile-gtk release.
- Popup menu on visible-wave button can activate per-waveform dialog box
- Logarithmic scale on Y axis working; on X axis it isn't quite there yet.
New in 20000108:
- Merged in guile and guile-gtk; the GUI is mostly written in guile now.
- Some additional improvements to reading of HSPICE input. Reading partial
files from simulations still in progress works for ascii .tr0 files.
Changes included in version 2.0.4
---------------------------------
- Fixed printing under windows.
- You can now plot the real and imaginary parts of the
circuit input and output impedances
Changes included in version 2.0.3
---------------------------------
- Moved to Qt version 2.1.0
- The help browser is now integrated into the ViPEC application.
- Fixed a bug in calculating the circuit output impedance.
- Input and output impedances ouput to a graph now works.
Changes included in version 2.0.2
---------------------------------
- Improved data storage of graphs and Smith charts
- Double buffering implemented for drawing of graphs
and Smith charts to reduce flicker.
- Improved font management
- Fixed display bug in Table view
- Fixed bug with output to 2 port parameter files under Windows
- Added support for Group Delay, see help files for more details
as well as sample circuit: group_delay.ckt
ACS 0.27 release notes (06/03/2000)
New features:
1. BSIM3 model, DC.
They work for AC and transient analysis, but only the DC effects
actually work. The next release should have the charge effects. For
now, it fakes it with Meyer's model.
2. A first cut at a model compiler, to aid in development of new
models. Models are described in a ".model" file, which is processed
to automatically generate the ".h" and ".cc" files. This version
fully handles the ".model" statement part of it, but leaves the device
and common sections the old way. Eventually, the entire process will
be automated. The old way still works.
3. "Fit" behavioral modeling function, which fits a curve to a set of
data. You can specify the order of the fit, which is piecewise
polynomials. For now, the order may be 1 (linear, like PWL) or 3
(cubic splines). You may also specify the boundary consitions.
4. More probes.
Some things that are partially implemented:
1. Internal element: non-quasi-static poly-capacitor. It is needed by
the BSIM3 and EKV models. Eventually, it will be available as a
netlist item, but not yet.
Bug fixes:
1. PWL could fail if there were duplicate points at the beginning. It
still does, but gives a reasonable error message.
2. Some "dot commands" were ignored if there were spaces before the
dot. This was particularly annoying if the line was supposed to be
".end" which should make it exit. It didn't, leaving it in
interactive mode, a major annoyance in a script.
Other improvements:
1. There is a change to the way integration in capacitors is done. It
is now strictly based on charge (i = dq/dt). The old version was
based on capacitance (i = C * dv/dt) which is strictly incorrect. The
dC/dt term was missing (i = C * dv/dt + v * dC/dt). This is a
non-issue when C is constant.
2. More documentation on internals.
Changes that I think are improvements, but some may disagree:
1. The command line is a little different. In the old version,
"acs file" would run it, and whether it exited or not depended on
whether there was an ".end" line. Now, by default, it just loads the
file in preparation for interactive use. If you want batch mode, say
"acs -b file".
2. The regression suite is included in the standard distribution.
Changes that are not really improvements:
1. Due to the model compiler, the build process is a little more
complicated. To do a complete build, you must build the model
compiler first, then the simulator. If you are not making any new
models, you can probably get away with just building the simulator.
This will change in a future release.
Bugs:
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. The makefile does not set up the proper link for the model
compiler. You need to do it manually.
Hot items for a future release (no promises, but highly probable):
1. Charge effects in BSIM models. They are computed, but not loaded
to the matrix.
2. Completion of model compiler, and its documentation.
3. Completion of multi-rate.
4. Homotopy methods to improve convergence.
5. Transmission line accuracy and speed improvements, using a step
control mechanism similar to that used for capacitors.
6. Parameterized subcircuits and defined parameters.
7. A "trigger" element, so time dependent values can be triggered by
the circuit, as an alternate to simple time.
To reach me, try this email address:
aldavis@ieee.org
ACS ftp sites:
ftp://ftp.geda.seul.org/pub/geda/dist/acs-0.27.tar.gz
http://www.geda.seul.org/dist/acs-0.27.tar.gz
ftp://sunsite.unc.edu/pub/Linux/apps/circuits/acs-0.27.tar.gz
are (from the authors announcements):
--------------------------------
Icarus Verilog snapshot 20000721
--------------------------------
(first snapshot after the 0.3 release)
This snapshot adds no new features or language support, but is working
towards more precise interpretation of scheduling and value propagation
details.
The first thing I've done is redesign the internal Link structure that
is used to connect the internal netlist together. There are some aspects
of the nexos of a set of links that were carried by the Link class or
by external functions. These have been moved to the new Nexus class and
linking and structure has improved because of it.
This has led me to modify the handing of signal initial values. In practice,
the time-0 value of a net is a property of the nexus instead of the objects
that are connected together, so I have implemented it so, and in the
process fixed a bunch of initial value problems.
One new feature that is added is support for non-constant delay expressions.
Now, you can even have something like ``#($random%256) <statement>'' and
expect it to do what you think. (So now the telephone example in James
Lee's "Verilog Qickstart" actually works!)
I've added some missing support for various operators in constant expressions.
I've also added some more of the friends of $random for those folks who
do stochastic modeling.
Constant propagation carries some new bug fixes, and some new smarts. It
is for example able to detect a mux with a constant 'bz input and replace
it with bufif devices, and other clevernesses with logic reduction.
--------------------------------
Icarus Verilog snapshot 20000729
--------------------------------
Like I said, the `timescale compiler directive now more or less works.
You can now specify timescale for modules, and the compiler will figure
out a global design resolution and scale your time values to match. The
VCD dumps should reflect the chosen resolution automatically. Floating
point notation is not yet supported, we'll see if that turns out to be
a problem.
A problem with `timescale support is that the compiler will allow unitless
modules. This can happen if you have `timescale late in the source file.
The default unit is the not-very-intuitive 1s. Frankly, I don't like the
`timescale semantics for this sort of reason, but its an accepted
standard, so I'm stuck with it.
I've also added support for min:typ:max expressions. The compiler chooses
one of the three expressions at compile time, based on a compile time
switch. You can ask for min typ or max values via the "-Tmin" etc. switch
to the iverilog command. If you do not specify a switch, the compiler will
choose the typ values but print warnings. The -Ttyp switch will suppress
the warnings.
I have fixed yet more net initialization bugs. These are getting pretty
subtle, now, so you should have a hard time tickling any remaining errors
here. I've also fixed a nasty and subtle bug in event expression support.
This bug only happened when the design had many event expressions with
many conjunctions.
Although they are not ready for use, I have made some forward progress
with disable statements. I now at least elaborate them, so now I just need
to figure out how to make the run-time work out. That's the hard part,
I'm afraid.
--------------------------------
Icarus Verilog snapshot 20000805
--------------------------------
I've finally dealt with a problem that's been nagging at me for a while.
Until now, it has been possible that excessively clever hierarchical
references into and out of task scopes could confound symbol lookup.
I think I finally put that to rest, and in the process reorganized the
netlist format for holding task definitions. It should no longer be
possible to confuse name binding in Icarus Verilog.
Found and fixed a silly bug in elaborating e?a:'bz and e?'bz:a expressions
into bufifN devices. I got the sense of the enable wrong in one of the
cases. All fixed (and the test suite updated to catch this silly mistake:-)
tri0 and tri1 nets should now work properly. These are mostly a run-
time issue which I solved using resolution functions. This is actually
a technique that I borrowed from VHDL.
For those of you doing XNF synthesis, I fixed up my FF/RAM detector to
allow <= assignments in always blocks. This is in fact the preferred way
to describe DFFs as <= more accurately simulates their RTL nature.
Also found and fixed a few DOS \r\n line end issues in the lexical ana-
lyser and the preprocessor. We sometimes forget how tricky these line-
end problems can be, and compiler directives are the most susceptible.
This problem most likely occurs when you transport files from a DOS
environment. (The MAC folks haven't complained much, so either I got it
right for them, or Kato took care of the problems for me:-)
Changes since 9.0g are (from the NEWS file):
Changes in Dinotrace 9.0k 7/17/2000
Fixed bug with $comment after $enddefinitions. [Harunobu Miyashita]
Fixed Tempest reading signals over 128 bits. [Ta-Chung Chang]
This bug was introduced in 9.0i.
Fixed portability bug with Value Examine showing 0s. [Ta-Chung Chang]
Fixed Verilog reading with large time intervals. [Matthias Wenzel]
Changes in Dinotrace 9.0i 5/1/2000
Major speed improvement in reading Tempest traces.
All trace formats now have less processing when building busses from
individual bits. [Steve Hoover]
ASCII traces assume extra time so last line is not lost.
ASCII traces which had timestamps would not show the last state of the
bus, as Dinotrace did not guess at how long that last state was valid for.
Now, it looks at the smallest time step in the trace, and uses that
as a guess at the timescale. [Pani Kodandapani]
which takes entries of the format <make-definition-name>=<pkgname>. This
has not been added to MAKEFLAGS because (a) premature optimisation is the
root of all evil, and (b) because the .for loop used to implement this
shows the wrong results when multiple prefices are evaluated.
Modify all the package Makefiles to use EVAL_PREFIX, thereby simplifying
them considerably.
ALso simplify the logic to calculate the prefix as well.
package's prefix would not work as part of the environment specification
via MAKE_ENV (as it would not be executed in the correct directory).
Fix this by invoking pkg_info(1) directly, not via an intermediate make(1)
step - this is not as clean, but more effective (i.e. it works).
a bit more user-friendly.
Introduce a show-{gtk+,imlib,kdebase,qt1,qt2,xpm}-prefix target in
bsd.pkg.mk, and use "${MAKE} show-*-prefix" in package Makefiles.
Changes, from the authors release statement, are:
This release is a significant improvement over previous releases of
Icarus Verilog, including better language coverage, improved
synthesis, and increased performance.
This release adds to the 0.2 release support for Verilog-2000 style
parameters and parameter overrides, defparam, and localparam,
including proper handling of scoping rules. Also, strength modeling is
added, with support for strengths attached to gates and continuous
assignments.
Combinational user defined primitives have been added to complement
synchronous primitives that were already supported. Support for
primitives should now be fairly complete.
Force/release/assign/deassign syntax now works properly, allowing for
more sophisticated test bench design and debugging.
Bug fixes have been numerous and varied. This release of Icarus
Verilog is considerably more robust then previous versions, thanks to
diligent testing and bug reporting by users all over the world.
Add a new USE_LIBTOOL definition that uses the libtool package instead of
pkglibtool which is now considered outdated.
USE_PKGLIBTOOL is available for backwards compatibility with old packages
but is deprecated for new packages.
changes since last packaged snapshot are (from the authors announcements):
Icarus Verilog 20000527 Snapshot
----------------------------------
It's snapshot time!
<ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20000527.tar.gz>
This snapshot doesn't add any new features, but fixes a few bugs. I've
taken care of a bunch of bug reports with an eye towards getting this
polished up for a 0.3 stable release.
I fixed some problems with elaborating the condition expression of a
ternary operator. This was a long-standing bug that only happened in
structural (i.e. continuous assignment) situations.
I've also done some merging of event expressions. The netlist format makes
NetEvProbe and NetEvent objects for event expressions, and it was making
more then were needed. I've done some merging, though I have some more
things I can do on this front. I'll be working on it for the next snapshot.
I found a whole bunch of bugs with parsing expression lists, for example
module port expressions. The result is actually a smaller parser:-) So
module port expressions should be parsed and elaborated correctly, now.
In the vvm code generator, I've found some room to optimize the generated
code. I detect duplicate initialization of a nexus, and prevent the
excess code being generating. In one slightly degenerate example sent to
me, this change reduced the generated C++ by more then 6 times. I was
pretty amazed.
I've also slightly optimized the special case of behavioral assignments
from simple signal expressions. This removed a few lines of generated
code per assignment. This sort of thing helps compile time performance.
Icarus Verilog 20000512 Snapshot
----------------------------------
This is mostly a bug fix snapshot. No new features here, but I'm starting
to buff it up shiny for an upcoming 0.3 release. It looks like I'll be
starting to do release candidates soon, so test this snapshot hard, folks!
<ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20000519.tar.gz>
I re-implemented flip-flop and RAM synthesis, the new technique should
allow me to make much more complete synthesis. It's still not the nifty
full-scale synthesis I hope to do some day, but it should catch some of
the bigger synthesis problems.
I've also added to XNF synthesis the ability to detect start-up initial
values for flip-flip devices. This causes it to generate INIT= properties
for the devices as appropriate.
I've improved the VVM code generated by the t-vvm code generator. I've
managed to reduce the size of the code generated for some larger models
by 30%, and I should have improved run-time performance in the process.
This should help.
I've also found (thanks to bug reports) and fixed some module port issues.
I bet you can't dream up legal port binding that Icarus Verilog can't
handle:-) This issue should be taken care of.
VPI now includes the ability to set registers. I needed this to implement
a PNG image I/O module. I'm still working on that, I'll distribute it
separately when it is in better shape.
Various other bug fixes in iverilog and elsewhere. Several bug fixes
in the VVM runtime, including some support for the % operator.
I've done some updates to documentation to reflect some of the changes
since 0.2, so you can take a look at that too.
changes from the last packaged snapshot (from the authors announcement):
---------------Icarus Verilog 20000506 Snapshot------------------
A lot of internal reworking has been done on this, so there might be
problems with things like symbol binding. But I think this is much better
then the last snapshot. I am once again starting to think about a
stable release. I'll shoot for the end of May, so if there is anything
you want to see in that release, start pestering me.
The big job has been a rewrite of the symbol table that holds signals.
The previous elaboration and lookup code for signals/memories did not
work properly when hierarchical names were used in the context of tasks
and functions. Also, the old table kept all the signals is a single
lookup table that failed to take advantage of knowledge of the current
scope.
All that is changed. signals are now elaborated after parameters and
before processes, so all hierarchical accesses should work properly now,
no matter how contorted. I've also fixed some bugs with function/task
parameter passing.
I've also added some infrastructure for supporting system functions, and
I've added an implementation of the $random system function. This currently
uses the native random(3) C library function, but once I get access to the
standardized algorithm, I'll implement that.
There are also a few fixes to elaboration of ternary operators. They were
a bit touchy about result bit widths.
A few preprocessor bugs have been fixed, especially related to the
`ifdef/`endif tokens. People are all the sudden starting to use the
Icarus Verilog preprocessor, so some long-standing bugs have been caught.
The iverilog command had a few path problems fixed, and the remaining
necessary switches have been added. I really encourage people to start
using iverilog in place of verilog. The test suite now uses iverilog to
run the compiler, so should you. There is a man page.
The many bug fixes and changes since the last packaged snapshot
are (from the authors announcements):
Icarus Verilog 20000428 Snapshot
--------------------------------
This one clears up some pretty nasty and subtle bugs. If you've been
sending me bug reports, you're probably turning blue holding your breath
in anticipation of this snapshot. Breath in, Breath out.
Hooray, both force and release work properly. I'm happy about that,
release worked out a bit easier then I expected. These should be useful
to test bench designers.
The big news this past week, however, has been bug fixes. Lots of bug
fixes. I got lots of bug reports and I killed pretty nearly all of
them. There were lots of nasty icky problems with passing parameters
to/from tasks, especially when memory words were involved. I fixed up
a whole bunch of these, and now parameter passing should work pretty
will, modulus the few remaining bugs I'm not seeing yet.
The iverilog command is in better shape now, and I encourage people
to use it in place of the older "verilog" driver script. There is a
man page for iverilog, and it supports all the switches needed to do
simulation and synthesis. I would like people to start getting this
driver well tested and the bugs worked out, because it is going to be
the main driver come the next stable release.
Some neat new XNF features are happening. I synthesize identity compare
in XNF, and a few other missing operators. But the really neato part is
that I've taught Icarus Verilog to generate PIN records for module
ports, so that you can make XNF macros out of Verilog source. If you
elaborate a module that has ports, the XNF code generator will automatically
generate the necessary symbols so that external XNF tools can link the
generated output into larger designs. I've compared the XNF files from
Icarus Verilog with those generated by Abel, and they appear the same
to my eyes.
Icarus Verilog 20000421 Snapshot
--------------------------------
Bunches of bug fixes, and a few new features come with this snapshot.
This snapshot makes headway in both simulation and synthesis. I'm
also starting to make a big dent in my todo list for the 0.3 release.
The bunches of little bug fixes in this snapshot are a direct result of
bunches of bug reports this past week that I was able to deal with. If
you've been reporting bugs, this may contain your fix.
I redesigned the process implementation in the vvm backend, so the generated
code is a bit cleaner, and threads are lighter weight. And while I was at
it, fork/join now should work properly. I know there were a bunch of you
out there asking for this, so here it is.
I've incorporated into this release improved runtime support for integer
multiplication, it should now work now matter how incredibly enormous
you make the operands. Thanks to Chris Lattner for contributing the generic
multiply.
I've improved synthesis somewhat, there were some expressions in some
contexts that were not getting synthesized by the -Fsynth functor. This
is fixed, and I'm also starting to add some XNF specific optimizations
into the -Fxnfio functor. I do sensible things with identity compare,
for example.
I've added the program ``iverilog'' to be a new driver program written
in C instead of as a shell script. This driver supports the -tnull,
-txnf and -tvvm targets, as well as the -E flag that causes only the
preprocessor to be run. This should be interesting to those of you who
are looking for a working preprocessor. I'm still working on the -D and
the -I flags, but I expect this program to replace the verilog.sh script
before the 0.3 release.
Icarus Verilog 20000414 Snapshot
--------------------------------
All event handling is now complete. Yet another subject is behind me, and
on I go. By complete, I mean that named events, edge triggers, wait, and
lists of events all work. This took a little longer then I expected, so
some of the other things I wanted to work on had to wait.
As a side effect of event and thread scheduling work, I changed the way
that threads are generated in vvm. The result is that threads should be
a little faster at run time, and a lot faster at compile time. A *LOT*
faster at compile time. (Apparently, Verilog XL is still considerably
faster, but hey, I'm working on it.)
changes since the last packaged snapshot include:
Icarus Verilog 20000326 Snapshot:
--------------------------------
The VVM backend rewrite continues. More templates are gone, and the
bit functions have been pretty much rewritten. The vvm library now handles
bit values with strengths, and most of the devices to the right things
with those strengths.
The most obvious implication of this is that you can write multiple
drivers to a net and expect the values to be properly resolved, and in
particular the HiZ value works as it should. So I am well on the way to
completing strength modeling support.
What is still missing is support for strength specifications in the
Verilog source. Although the parser supports the strength related keywords,
they are not passed on to elaboration, or used to generate drivers with
the proper strengths. So that's in the works.
While doing all this VVM rewrite, I've made the generated code considerably
smaller. And of course fewer templates are used. The upshot of this is that
compiles of larger designs should go a whole lot faster. This is important
because people are using Icarus Verilog for increasingly larger designs.
On some larger examples, I've achieved more then 3X compile time improvement.
Icarus Verilog 20000409 Snapshot:
--------------------------------
Named events now work! Event object declarations and trigger statements
are fully supported, and blocking on a single event also works. I'm not
up to named events in event lists because I'm in the midst of redesigning
the way events on nets and regs are implemented. However, the common case
works fine, so there you are.
I've also added support for some more arithmetic operators. Division and
Modulus now work in many contexts, and are not far from working everywhere.
Also, comparison operators work in places they used to not.
There was a compile error in memory objects that managed to slip through
a couple snapshots, that I finally cured. The problem was pretty gross,
but somehow not quite tickled by my tests. Oh well.
I've integrated some VCD improvements from Anthony Bybell. Some of you
recognize the name as the author of GTKWave, so if he says VCD works like
so, then that's how VCD works:-) Anyhow, he fixed the VCD output to be
more portable, and also a bit smaller when vectors are involved. He also
fixed some bugs with multiple calls to $dumpvars.
- Make sure -Rpath is done correctly
- Make sure qt libs are found
- Make sure -lz -lpng -lSM are included as libqt needs functions
from these libraries.
components. This allows users of Qt to specify QTDIR=/path/to/qt instead
of having to patch all configure scripts and makefiles to look for alternate
names. This is the recommended approach from Troll Tech (Qt authors).
update pkgs which use qt1 to reflect this.
New features:
1. BSIM1, BSIM2 models -- DC only.
2. New elements:
trans-capacitor
voltage controlled capacitor
voltage controlled conductance
voltage controlled resistor
3. Optional new syntax, with type first so component labels can start
with any letter, and the choice of components is no longer limited by
the 26 letters. This was necessary for a clean syntax
for #2.
4. Some new parameters on existing devices, also a side
effect of the BSIM work.
5. The manual in HTML form. The manual source is still in LaTeX,
which can be used to generate HTML, PDF, Postscript, or many other
formats.
Bug fixes:
1. An error causing truncation error to be underestimated has been fixed.
Other improvements:
1. MOSFET model evaluation is a little faster, due to use of one of
the new elements to replace several old ones. I have seen 40%, but
20% is more likely. The improvement is most evident on busy circuits,
where the ACS speed enhancements based on latency exploitation
contribute more overhead than their value, that is .. the type of
circuit that has run faster in Spice than ACS.
2. More documentation on internals.
Changes that I think are improvements, but some may disagree:
1. Truncation error based step control is disabled when Euler's method
is selected. The justification for this is that the reason for
selecting Euler's method is to avoid the artifacts of high order
methods on "stiff" poles. Without this change, a "stiff" pole would
cause an unreasonably small step size. This did not appear to be much
of a problem in the old release because the use of an incorrect
formula for estimating truncation error. A "stiff" pole is one that
has a response so fast it can be thought of as instantaneous.
2. The "help" command, with its 4 year old help file, has been
removed. The concept is really obsolete. With the HTML form of the
manual, a full online manual is a better replacement.
Notable changes since the last pkg are (from the snapshot announcement):
Parameters are complete.
What this means is that I finally got around to supporting defparam,
and while I was at it I rewrote the entire parameter handling and added
the parameter support included in 1364-2000.
I have rewritten major portions of the VVM backend. The vvm_nexus class
has been introduced to the fray, and all the device implementations in
the VVM library now use the nexus to drive and receive values. An advantage
of this scheme is that the t-vvm backend code (in ivl proper) is simpler,
and so is the generated C++ code.
I also removed most of the template classes. This proved to be a huge
compile-time benefit (though compiling twice as fast really only matters
for large programs) and it doesn't seem likely to hurt run-time performance.
A few remain, either because they seemed harmless (the N-wide logic gates)
or I couldn't yet figure out a good way to replace them (vvm_bitset_t).
A side benefit of this is that the vvm library may now be a modeling
library that ordinary humans can use to write their models in C++. This
may provide the unexpected benefit of heading me towards incremental
compilation of designs. So who was it who was beating me over the head
asking for that?-)
I also fixed a few minor problems with the preprocessor. Those of you
who reported problems with `includes and `defines should check this out.
Dinotrace is a tool designed to aid in viewing Verilog Value Change
Dump (.vcd), ASCII, Verilator, Tempest CCLI, COSMOS, Chango and Decsim
Binary simulation traces. It is optimized for rapid design debugging using
X-Windows Mosaic.
verilog-current pkg to track development snapshots.
This version has minor bug fixes over the previous snapshot package. Notable
$display of a memory element now works correctly and a bug in $readmemb has
been fixed.
Gwave is a viewer for spice-like simulator output and other analog data
Gwave can read several file formats. It attempts to guess file formats
based on filename, and then tries all file formats until one succedes.
These file formats are known:
CAzM transient output (*.[BNW])
HSPICE binary and ascii formats (*.tr0, *.sw0, *.ac0)
Spice2 and Spice3 "raw" output (*.raw)
An ascii format with whitespace-seperated columns and column headings,
such as that produced by ACS (Al's circuit simulator). (*.acs, *.asc, *.ascii)
The "Export Postscript" and "Export PNM" options on the main File menu
provide the rudiments of output for inclusion in other
documentation. They and simply write out files called gwave_out.ps and
gwave_out.pnm into the current directory. In the future, a dialog box
will allow configuring the print and export output.
Changes include:
* New dialog boxes by Matt Ettus:
- A much improved attribute edit dialog box
- A multiple attribute edit dialog box
* Improved Hierarchy Support:
- Hierarchy/Down Schematic
- Hierarchy/Down Symbol
- Hierarchy/Up
* Text alignment.
* Attributes are now required to have no spaces besides
the equals sign on each side. This shouldn't cause
any problems for anybody.
* Bunch of updates to the various gnetlist backends
(basically all submitted changes have been integrated).
Integration of JM Routoure's PCB backend work (Thanks!).
Bug fixes and improvements by Matt Ettus, Stefan
Petersen and Bas Gieltjes.
* Added a bunch of contributed symbols. Thanks to
all that have contributed! There are now 566 symbols
in the library.
* Documentation. There are the beginnings of docs now.
Here's the current list:
attributes.txt -- Master attribute list
fileformats.html -- gEDA file formats
gschem.txt -- The start of a serious user's
guide keymapping.html -- Stefan's keymapping
document netattrib.txt -- A HOWTO on the net=
attribute symbols.html -- The ever useful symbol
creation guide
* Bug fixes and improvements to some of the utils.
* Lots and lots of bug fixes (and bug introductions).
Cascade is a program for analyzing the noise and distortion
performance of a cascade of elements in an electronic system. A
typical application of cascade is the analysis of a receiver. A text
description of the receiver block diagram consisting of things like
amplifiers, mixers, and filters is entered into cascade. Each element
is characterized by its gain and optionally noise figure, and third
order intercept point. The program then analyzes the system and
produces a report detailing the performance at each stage.
A summary is produced which shows the relative contributions to the
total system performance of each block. This allows easy
identification of what limits system performance.
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
compiler, compiling source code writen in Verilog (IEEE-1364) into some target
format. For batch simulation, the compiler can generate C++ code that is
compiled and linked with a run time library (called "vvm") then executed as
a command to run the simulation. For synthesis, the compiler generates
netlists in the desired format.
The compiler proper is intended to parse and elaborate design descriptions
written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
complex standard, so it will take some time for it to get there, but that's
the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
and some -1999 features will creep in.
ACS is a general purpose circuit simulator. It performs nonlinear
dc and transient analyses, fourier analysis, and ac analysis
linearized at an operating point. It is fully interactive and
command driven. It can also be run in batch mode or as a server.
The output is produced as it simulates. Spice compatible models
for the MOSFET (level 1,2,3,6) and diode are included in this
release.
Since it is fully interactive, it is possible to make changes and
re-simulate quickly. The interactive design makes it well suited
to the typical iterative design process used it optimizing a circuit
design. It is also well suited to undergraduate teaching where
Spice in batch mode can be quite intimidating. This version, while
still officially in beta test, should be stable enough for basic
undergraduate teaching and courses in MOS design, but not for
bipolar design.
In batch mode it is mostly Spice compatible, so it is often possible
to use the same file for both ACS and Spice.
enhancements. Most notably, gEDA was split into several independent
modules, using a common library 'libgeda'. These modules are now separate
packages with geda now becoming a meta package.
note that the version number is the date when I grabbed the
sources. There is no "official" version included in the
sources.
Xchiplogo reads an ascii bitmap file, and converts it into a
magic or cif file. It is a handy program for creating logos
of text or graphics for putting on VLSI chips. At the
moment it accepts the B&W dithered format of XV as the
input. It has got quite a few options for resizing and get-
ting rid of many design rule errors that can be found in the
bitmap file. It has a smoothing, before and after an error
correction step. The error correction step is pretty simple
,don't expect miracles, but it works quite fine and spe-
cially for text gives a reasonable output.
- fixed program version number reported when spice is run to make it consistent
with the version of the program.
- several patches to fix compilation warnings due to missing header files and
some inconsistent variable types.
- broke out previous patch-aa which patched several files into 1 patch per file.
- fixed some code which returned the address of a local char array variable.
- added GNU readline support (a huge improvement in the interface)
- changed USE_X11BASE to USE_X11. No reason to install into X11BASE.
- removed 'x' target from package Makefile
Important changes are:
- Now uses gtk+-1.2.2
- A bunch of bug fixes.
- Added a coordinate window to gschem
- Integration of contributed symbols.
- Latest Jerry O'Keefe's gmk_sym integrated
- Mike Jarabek's verilog gnetlist backend integrated
- Jamil Khatib's latest gschcheck
build a binary package with this definition would fail as the PLIST is
not correct.
If a package's documentation is overwhelming, it should arguably be handled
in a separate pre-requisite documentation package.
around my /usr/pkg/bin, and thus tex never got installed, and the build
blew up. I don't believe any older pkgs install "tex", so this should be
a safe bet.
- New, optional Makefile variable HOMEPAGE, specifies a URL for
the home page of the software if it has one.
- The value of HOMEPAGE is used to add a link from the
README.html files.
- pkglint updated to know about it. The "correct" location for
HOMEPAGE in the Makefile is after MAINTAINER, in that same
section.
