pkglint -Wall -r -F cad
Manually fixed the indentation in cad/ghdl/Makefile because SITES.* was
(by the current definition) not long enough to count as an outlier line,
and because of this, all other lines were aligned to that line.
library dependencies (caused by the tcl/tk update to 8.4). Use tclConfig.sh
to determine which libraries are really needed. Noted in last kristerw@'s
bulk build.
jmmv at menta dot net.
TkGate is a digital circuit editor and simulator with a Tcl/Tk based
interface. TkGate includes a large number of built-in devices
including basic gates, memories, ttys and modules for hierarchical
design. The simulator can be controlled either interactively or
through a simulation script. Memory contents can be loaded from
files, and a microcode/macrocode compiler (gmac) is included to create
tkgate memory files from a high-level description. The simulator
supports continous simulation, single step simulation (by clock or
epoch) and breakpoints. Save files are in a Verilog-like format.
TkGate also includes a number of tutorial and example circuits which
can be loaded through the "Help" menu. The examples range from a
simple gate-level 3-bit adder to a 16-bit CPU programmed to play the
"Animals" game.
TkGate has a multi-langauge interface with support for English,
Japanese, French and Spanish.
