From the NEWS file:
* Changes in Dinotrace 9.1i 03/07/2003
*** Display values with appropriate leading 0s. [Dan McMahill]
*** Fix 0 extension of verilog values. [Dominik Strasser, Bill Welch]
Transcalc is an analysis and synthesis tool for calculating the
electrical and physical properties of different kinds of RF and
microwave transmission lines.
Transcalc was somewhat inspired by the functionality of Agilent
Technologies' commercial program linecalc. Transcalc aspires to be
more functional in the long run and well-documented with appropriate
references to formulas that are used. Transcalc is built using the
GIMP toolkit (GTK) for its GUI interface.
For each type of transmission line, using dialog boxes, you can enter
values for the various parameters, and either calculate its electrical
properties (analyze), or use the given electrical requirements to
sythesize physical parameters of the required transmission line.
Available transmission lines (this list will expand with subsequent
releases):
* microstrip
* rectangular waveguide
* coax
* coupled microstrip
* You cannot compile with backend anymore, switch is removed. In last
release this caused compilation error due to bit rot.
* Drawing of arcs is a constant headache. Mark Whitis found another
case that I had missed out. Clockwise arcs all of a sudden started
to be drawn as counter-clockwise.
* Arcs with very small angle differences could either be a complete
circle or a very small part of an arc. Calculating the angles with
integers wasn't sufficient, anyhow. They are now doubles all the way.
* Aperture macro primitive 1 was a _filled_ circle.
* Image rotate used to cause warnings that it wasn't implemented. Now
if the file has an image rotate on zero degrees there is no warning
(yes I've seen it).
* Dan McMahill discovered that if you tried to swap with an unused layer
gerbv segfaulted.
* Peter Monta submitted patch for incremental coordinates.
* No traces of Guile left...
Makefiles simply need to use this value often, for better or for
worse.
(2) Create a new variable FIX_RPATH that lists variables that should
be cleansed of -R or -rpath values if ${_USE_RPATH} is "no". By
default, FIX_RPATH contains LIBS, X11_LDFLAGS, and LDFLAGS, and
additional variables may be appended from package Makefiles.
Quick summary of changes:
- works with guile-1.6.3 now
- Norwegian/Danish/German character fixes
- PNG output now has some of the objects appearing to have the right thickness.
- added Russian translation
- bug fix in postscript output
- non-applicable menu choices are now greyed out
- fixed PADS netlist output bug
- added several components to library
- added multisheet refdes renumber utility
- several other bug fixes.
The previous version was extremely out of date and the distfile is no
longer available.
Many, many changes since the last packaged version. New 'tuner' feature
added. New models added. Several bug fixes too numerous to list.
in recent bulk builds.
Release covered-20021214 made. This release is a bug fix release. See list below
for details. Bugs that lead to infinite looping in the score command and segmentation
faults should now be cleared up. Please let me know if there are any other bugs that
need to be addressed before first stable release. Development documentation updated
to match changes in files. Regression suite has been updated quite a bit from last
time. There are now over 125 diagnostics in the regression suite (my goal was to
write about 100 before first stable release).
- Segmentation fault fixes in report command
- Parser can now handle all net types (not just wire). Diagnostics added to regression
suite to verify their proper handling.
- Parser updated to handle net declaration assignments (e.g., wire a = b & c;).
Diagnostics added to verify proper handling.
- Added human-understandable error messages in parser to help identify file and
line number along with a quasi-helpful error message description.
- When parser error is found, Covered exits after parsing phase without continuing
to write CDD file.
- Fixed bug where a multi-bit select expression existed in a module that was
instantiated more than once. Assertion error fired in this case.
- Updated regression suite for VCS testing.
- Fixed bug where parameters were used in modules that were instantiated more than
once.
- Fixed bug that dealt with parameters (see param6.1.v for test case).
- Fixed bug where a delay statement was the last statement in a statement block used
by Covered. Added diagnostics to verify correct behavior.
- Fixed infinite loop problem with db_add_statement function.
- Fixed infinite loop problem with statement_set_stop function.
- Fixed bug with parsing order. When an instance is found for a module that has
already been parsed, the instance was incorrectly being handled. Bug replicated
with instance6.v diagnostic.
- Fixed output of edge-triggered events to add @(...) around the expression (they
were easily confused with other code that could exist on the same line).
- Fixed bug in parser to not allow module to be parsed more than once.
- Fixed bug that lead to an assertion error (see instance6.1.v for test case).
- Fixing bug with calculating list and concatenation lengths when MBIT_SEL
expressions were included.
- Changed Covered's handling of -y directories. Before, all files in these directories
were fed into the parser to look for missing modules. Now, when a module is needed,
the module name is used to find the matching filename in the -y list (basically,
the -y option works like the -y option in Icarus Verilog and VCS). This fix really
streamlined the parsing phase and fixed several bugs.
- Memory declarations are now properly ignored (produced segmentation fault previously).
- Fixed report command to display all lines and expressions in order according to
their line number (the problem is REALLY fixed now).
- Removed hierarchical references from being scored.
All in all, you should notice a huge improvement in the parsing speed, syntax errors are
reported better, more Verilog syntax should be handled properly, the score command will
run a bit faster than before, and the reports should be a bit easier to read. Segmentation
faults and assertion errors should become lesser in number (if not gone altogether?).
I am feeling pretty confident that we are getting close to a stable release as I have
been able to generate a CDD file for a chip that is millions of gates in size (CDD file
was created in the range of 30 - 45 seconds!) Keep the bug reports coming. I have some
things to work on for next release already.
This is the first packaged (in pkgsrc) snapshot after the verilog-0.7
release.
This snapshot adds preliminary support for real variables to the language
to the features already found in verilog-0.7.
Many improvements such as support for mixed dielectric systems and several
bitmap generators for common structures to allow quick application of the
tool. Several bug fixes as well. Voltages outside a shield are set to zero
which fixes a reported result in older versions. Many other improvemnts
and bug fixes are listed in the ChangeLog in the distfile.
have it be automatically included by bsd.pkg.mk if USE_PKGINSTALL is set
to "YES". This enforces the requirement that bsd.pkg.install.mk be
included at the end of a package Makefile. Idea suggested by Julio M.
Merino Vidal <jmmv at menta.net>.
This release represents many bug fixes, expanded language coverage,
greatly enhanced xilinx fpga synthesis and several performance enhancements.
The complete list is rather long.
GDSreader - simple Calma (GDSii) parser/printer tool.
This software has as target the printing/plotting/displaying of Calma (GDSii)
files without using true layout editors. I had once to visualize an unknown
Calma file and customizing LEdit or Magic (the two layout editors I had access
to) was so difficult that I decided to write this program.
Current status:
- gdsreader is in an alpha stage and you should not expect too much from it;
- the Calma files are almost completely parsed (had no layout example that
makes use of BOX/NODE elements);
- given a Calma structure name, a PostScript file and a HPGL/2 file are
generated. The way each layer is handled is controlled by an ASCII
configuration file. The properties that can be set are color, fill (only
solid is supported), hatch (simple or cross, the angle and spacing are user
customizable too).
In order to produce an useful PostScript output, you need to write a
configuration file (default is .layers.config). The one you'll find with the
distribution is suitable for the Calma example test.gds (an actual Bandgap
reference).
This represents many many improvements and bug fixes. A few items to
note are that the attributes used by the symbol library have been
greately cleaned up and unified. You may want to run gsymupdate and gschemupdate
if migrating from older versions of the tools.
This is a development snapshot. Packages of the released/stable
versions will be imported as 'cad/covered' when available.
Covered is a Verilog code coverage analysis tool that can be useful
for determining how well a diagnostic test suite is covering the
design under test. Typically in the design verification work flow, a
design verification engineer will develop a self-checking test suite
to verify design elements/functions specified by a design's
specification document. When the test suite contains all of the tests
required by the design specification, the test writer may be asking
him/herself, "How much logic in the design is actually being
exercised?", "Does my test suite cover all of the logic under test?",
and "Am I done writing tests for the logic?". When the design
verification gets to this point, it is often useful to get some
metrics for determining logic coverage. This is where a code coverage
utility, such as Covered, is very useful.
Please note that this package is a development snapshot and while it
contains the latest and greatest features, it may be buggy as well.
There is a seperate package which is made of the stable releases.
