TNT-MMTL, the Multilayer Multiconductor Transmission Line 2-D and 2.5-D
electromagnetic modeling tool suite, generates transmission parameters
and SPICE models from descriptions of electronics interconnect
dimensions and materials properties.
MMTL programs and supporting libraries and documentation have been
under development at the Mayo Clinic since the mid-1980s. The programs
were developed under government sponsored electronics research
programs in the Special Purpose Processor Development Group
(SPPDG). They have been employed extensively at Mayo and distributed
to some government agencies and research collaborators. At the
beginning of 2004, we decided to release the TNT graphical front-end
and MMTL programs as free software under the GNU General Public
License (GPL). Technically, MMTL programs are in the class of 2-D and
2.5-D "field solvers", which convert dimensions and materials
properties into electronic design parameters. The MMTL suite consists
of several programs, including lossy, loss-free, quasi-static, and
full-wave simulators. Circuit parameters are computed by either the
method of moments (MOM) or finite element methods (FEM). Basic
per-unit-length parameters are generated by the simulator, and can be
converted into HSPICE W-element models. MMTL is similar in many ways
to commercial field solver products which typically cost thousands of
dollars.
All library names listed by *.la files no longer need to be listed
in the PLIST, e.g., instead of:
lib/libfoo.a
lib/libfoo.la
lib/libfoo.so
lib/libfoo.so.0
lib/libfoo.so.0.1
one simply needs:
lib/libfoo.la
and bsd.pkg.mk will automatically ensure that the additional library
names are listed in the installed package +CONTENTS file.
Also make LIBTOOLIZE_PLIST default to "yes".
The big news is that module instance arrays now work. Gate and UDP
instance arrays have worked for a while, but module instance arrays
were more tricky because of the scope arrys they create. The issues
have been dealt with, and module instance arrays are now supported.
An interesting but subtle set of bugs in the evaluation of ternary
expressions has been fixed. The problems expressed themselves when the
condition expression was constant.
Degenerate wait statements now work properly.
The @* syntax apparently missed sensitivities in l-value expressions
of assignment statements. This led to subtle bugs in carefully crafted
bits of code.
Verilog attributes are properly parsed in a few more contexts. Also,
some specify syntax cases have been fixed.
Some minor spelling and documentation errors have been fixed, along
with assorted compiler warnings.
- distfile has moved
- license has changed. Patches are the result of de-fuzzing the
old patches since the new source files have the new (less restrictive)
license.
========================================================================
Release Notes for PCB snapshot 20040903
========================================================================
- enable -Wall when compiling with gcc. Many compiler warnings have
been fixed.
- add a short man page which refers the user to the real documentation
- Added ExecuteFile(file) action which allows the execution of several
actions contained in a text file.
- Added -script <file> flag which specifies a file containing actions
to be executed upon startup.
- Various documentation improvements
- Protect some gcc extensions with tests for gcc. This allows
compilation with the IRIX c compiler.
- Add support for a background image in the drawing area which can
help in importing a layout from a scanned image.
- Updated the ~geda library 150 and 300 mil width SOIC packages
to remove silk on pads and to more closely follow the IPC
recommendations
- Added support for menu accelerators.
- segfault when breaking apart an element with no element selected
bug fixed.
- autorouter improvements
- added more 400mil DIP packages to ~geda library
- fix a trace optimizer bug which produced a segfault
- other various bug fixes
changes include:
Added support for the `default_nettype directine, including the
default net type of "none", which turns off implicit net declarations.
Signed /, % and >>> in nets should now work properly. Also, various
operators of all sorts applied to constants have been improved.
Ranges now work on localparams.
Added the system tasks $unsigned, $is_signed, $mti_random and
$mti-dist_uniform. See the make README.txt for a description of these
system functions. Also, flesh out the standard random number
generators to match the sequences generated by other compilers.
There is now an "sft" file that describes to the compiler the return
value of system functions. This allows user supplied system functions
to have interesting return types. See "SYSTEM FUNCTIO TABLE FILES" in
the iverilog man page. Include a sft file for the system functions,
and move the system functions over to that mechinism.
Fix the behavior of $fgets in tight fitting result buffers.
A variety of compilation environment fixes have been added. These
involve configure scripts and Makefiles.
And of course a variety of other bug fixes, and so on and so forth.
which are the full option names used to set rpath directives for the
linker and the compiler, respectively. In places were we are invoking
the linker, use "${LINKER_RPATH_FLAG} <path>", where the space is
inserted in case the flag is a word, e.g. -rpath. The default values
of *_RPATH_FLAG are set by the compiler/*.mk files, depending on the
compiler that you use. They may be overridden on a ${OPSYS}-specific
basis by setting _OPSYS_LINKER_RPATH_FLAG and _OPSYS_COMPILER_RPATH_FLAG,
respectively. Garbage-collect _OPSYS_RPATH_NAME and _COMPILER_LD_FLAG.
gnetman is a program which currently supports advanced SPICE
netlisting from gschem (part of the gEDA tool suite). The
primary use so far has been for complex IC design. Supported
features include multi-level hierarchy, instance arrays, and
buses. If you're just doing flat designs for PC boards or
smaller SPICE simulations, the usual path is to use the spice-sdb
netlister for gnetlist instead.
The long term goal of gnetman is far greater. Two projects under
consideration include a schematic generator, and a technology
mapping back-end for Icarus Verilog. Basically, gnetman is a
netlist manipulation database well suited for low-level
manipulation of netlists.
library dependencies (caused by the tcl/tk update to 8.4). Use tclConfig.sh
to determine which libraries are really needed. Noted in last kristerw@'s
bulk build.
* Release Notes for Icarus Verilog Snapshot 20040606
Ports of primitives can bind by name as well as by position. Also
support Verilog 2001 style port declarations for primitives.
System function return types can now be specified by system function
table files. System Function Table Files are described in the iverilog
man page. Also include better system function return types in VPI.
Non-blocking assign of real values to real variables now works.
Properly handle nul strings ("") as 8bit values. This is a weirdness
legacy of XL.
Fix some synthesis problems for logical OR and logical AND. Bitwise OR
and AND were fine. These fixes affected simulation as well.
Handle wait statements with all sorts of constant values. These are
sometimes weird, bug legal.
Handle Negative value reals, and a few other bugs related to real
numbers.
Change internal use of identifiers to perm_strings for better
performance.
Functions returning unsupported types now generate error
messages. Previously, they would quietly generate bad
code. Infrastructure is also added to eventually support arbitrary
function return types.
Better compile-time support for Cygwin vs mingw32.
The ipal target is removed from this source. (ipal is now an add-on
package that is compiled seperately.)
========================================================================
Release Notes for PCB snapshot 20040530
========================================================================
This has been an exciting 3 months for PCB. Many improvements have
been made in the program as well as additions and improvements to the
footprint library. Thanks to everyone who has provided feedback,
patches, etc.
----------------------
Additions/Improvements
----------------------
- Expanded DRC checking
- "Realtime" DRC checking
- DRC settings are now stored in the board fle
- Centroid (X-Y) and bill of materials output
- Dynamic menus. Users can now customize the menus via a
site-wide, per-user, or per-project menu resource file.
- Significant improvements to autorouting of congested designs.
- Autorouter can now use power planes.
- Improved appearance in autorouter output.
- Silk on pads/pins is clipped in RS-274-X output
- Ordering is preserved when writing output files so that diff
may be effectively used on pcb files.
- The autoplace feature now actually works
- Added ToggleVisibility action
- Most of the database is now kept in rtrees which avoids linear
searches. This speeds up operation significantly.
- Added SetFlag, ClrFlag, ChangeFlag actions
---------
Bug Fixes
---------
- pin/pad bounding box calculation fixed. Components can
now be placed closer to the edge of the board.
- miter trace optimization bug.
- Fix bug with pins which are enclosed by multiple polygons.
- Shorts to unnamed elements and pins are handled correctly.
- Various memory leaks fixed.
- Fixed some bugs with a really high zoom.
- Fixed default media selection in postscript print dialog
- Fix some DRC bugs with square pins.
------------------
Footprint Library:
------------------
- Added SOJ footprint family (~geda library)
- Added CTS series 742/3/4/5/6 resistor pack footprints (~cts library)
- Added PKG_CONNECTOR_DIL macro to let the HEADER*_1 footprints work
(~geda library)
- Correct the SDIP footprints (~geda library)
- Correct some Minicircuits footprints (~minicircuits library)
- Correct some panasonic footprints (~panasonic library)
- Change refdes silk size for sockets (~johnstech library)
- Increase soldermask relief on some mounting holes
(~johnstech library)
- Convert the COMMON_SMT_DIL_MIL and COMMON_SMT_DIL_MM macros
used by several other libraries to the hi-res format.
- Correct pin count on 100 pin QFP packages (100 not 72)
(~geda library)
- Correct pin count on HEADER60_2 (60 not 50) (~geda library)
additions/changes since gerbv-0.15:
* projects: you can save and load setups in what I call projects.
* GTK+ 2 support
* Now you can invert a layer by the push of button. Basically.
* When gerber files were defined with omit trailing zeros, gerbv could
parse them very bad. Now it should work better.
* Aperture macros did not handle exposures at all. Now they do a better
work. Some thermals are defined from their CAD program as a sequence of
aperture macros instead of just using aperture macro 7. They are drawn
better now.
* Handles tool tables when drawing drill files thanks to Dimitri. See man
page for more info.
