12 lines
751 B
Text
12 lines
751 B
Text
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
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compiler, compiling source code writen in Verilog (IEEE-1364) into some target
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format. For batch simulation, the compiler can generate C++ code that is
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compiled and linked with a run time library (called "vvm") then executed as
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a command to run the simulation. For synthesis, the compiler generates
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netlists in the desired format.
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The compiler proper is intended to parse and elaborate design descriptions
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written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
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complex standard, so it will take some time for it to get there, but that's
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the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
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and some -1999 features will creep in.
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