d83949aa37
pkgsrc packages altered: - cad/MyHDL-gplcver - cad/MyHDL-iverilog - cad/py-MyHDL upstream changelog ------------------------ What’s new in MyHDL 0.10 The block decorator Rationale The historical approach for hierarchy extraction in MyHDL suffers from significant issues. This results in complex code, a number of non-intuitive API concepts, and difficulties for future development. In this release, a new block decorator is introduced to address these issues. For an in-depth discussion, see mep-114. API block() :noindex: The block decorator enables a method-based API which is more consistent, simplifies implementation, and reduces the size of the myhdl namespace. The methods work on block instances, created by calling a function decorated with the block decorator: @block def myblock(<ports>): ... return <instances> inst = myblock(<port-associations>) # inst supports the methods of the block instance API The API on a block instance looks as follows: <block_instance>.run_sim(duration=None) Run a simulation “forever” (default) or for a specified duration. <block_instance>.config_sim(backend='myhdl', trace=False) - Optional simulation configuration: - backend: Defaults to ‘myhdl - trace: Enable waveform tracing, default False. <block_instance>.quit_sim() Quit an active simulation. This is method is currently required because only a single simulation can be active. <block_instance>.convert(hdl='Verilog', **kwargs) - Converts MyHDL code to a target HDL. - hdl: ‘VHDL’ or ‘Verilog’. Defaults to Verilog. - Supported keyword arguments: - path: Destination folder. Defaults to current working dir. - name: Module and output file name. Defaults to self.mod.__name__. - trace: Whether the testbench should dump all signal waveforms. Defaults to False. - testbench: Verilog only. Specifies whether a testbench should be created. Defaults to True. - timescale: timescale parameter. Defaults to ‘1ns/10ps’. Verilog only. <block_instance>.verify_convert() Verify conversion output, by comparing target HDL simulation log with MyHDL simulation log. <block_instance>.analyze_convert() Analyze conversion output by compilation with target HDL compiler. Backwards compatibility issues In the 0.10 release, the old API still available next to the new API based on the block decorator. It is likely that the old API will be deprecated in a future release, resulting in backwards incompatibility for legacy code. Therefore, users are encouraged to start using the new API in their development methodology. |
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adms | ||
atlc | ||
boolean | ||
cascade | ||
cgi-wcalc | ||
covered | ||
dinotrace | ||
dinotrace-mode | ||
diylc | ||
eagle | ||
electric | ||
fastcap | ||
fasthenry | ||
felt | ||
freehdl | ||
gdsreader | ||
geda | ||
gerbv | ||
ghdl | ||
gnetman | ||
gnucap | ||
gplcver | ||
gsmc | ||
gtk1-wcalc | ||
gtk2-wcalc | ||
gtkwave | ||
iverilog | ||
kicad | ||
kicad-doc | ||
kicad-footprints | ||
kicad-i18n | ||
kicad-lib | ||
klayout | ||
librecad | ||
libwcalc | ||
magic | ||
mcalc | ||
mex-wcalc | ||
mpac | ||
MyHDL-gplcver | ||
MyHDL-iverilog | ||
nelma | ||
ng-spice | ||
ntesla | ||
oce | ||
openscad | ||
p5-gds2 | ||
pcb | ||
py-gds | ||
py-gdscad | ||
py-MyHDL | ||
py-simpy | ||
qcad | ||
qcad-partlibrary | ||
sci-wcalc | ||
solvespace | ||
spice | ||
spiceprm | ||
stdio-wcalc | ||
tkgate | ||
tnt-mmtl | ||
transcalc | ||
verilog-mode | ||
veriwell | ||
wcalc | ||
wcalc-docs | ||
xchiplogo | ||
xcircuit | ||
Makefile |