pkgsrc/cad/verilog-mode
2022-05-14 22:25:32 +00:00
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distinfo cad: Replace RMD160 checksums with BLAKE2s checksums 2021-10-26 10:04:09 +00:00
Makefile Bump all elisp packages for the CONFLICTS change. 2022-05-14 22:25:32 +00:00
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