dmcmahill 1c2773e731 update to verilog-0.4. ... from the authors announcement: So many things have changed since version 0.3 that there is no point in listing them. There have been tons and tons of bug fixes and the language coverage is better, and so on and so forth. It's just so very much better then version 0.3:-) speaking as a user, some of my personal favorites are: - support for signed variables - iverilog now gives correct return codes (which makes 'make' much happier) for a more complete list, the commit messages for pkgsrc/cad/verilog-current/Makefile contain the changes for each development snapshot between verilog-0.3 and verilog-0.4		2001-02-04 15:36:49 +00:00
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files	update to verilog-0.4.	2001-02-04 15:36:49 +00:00
patches	update to verilog-0.4.	2001-02-04 15:36:49 +00:00
pkg	update to verilog-0.4.	2001-02-04 15:36:49 +00:00
Makefile	update to verilog-0.4.	2001-02-04 15:36:49 +00:00