pkgsrc/cad/verilog/PLIST
dmcmahill fe2c5b1c95 update to verilog-0.7
This release represents many bug fixes, expanded language coverage,
greatly enhanced xilinx fpga synthesis and several performance enhancements.
The complete list is rather long.
2002-12-15 01:57:12 +00:00

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@comment $NetBSD: PLIST,v 1.3 2002/12/15 01:57:12 dmcmahill Exp $
bin/iverilog
bin/iverilog-vpi
bin/vvp
include/acc_user.h
include/ivl_target.h
include/veriuser.h
include/vpi_user.h
lib/libveriuser.a
lib/libvpi.a
lib/ivl/fpga.tgt
lib/ivl/ivl
lib/ivl/iverilog.conf
lib/ivl/ivlpp
lib/ivl/null.tgt
lib/ivl/system.vpi
lib/ivl/vvp.tgt
man/man1/iverilog.1
man/man1/iverilog-vpi.1
man/man1/vvp.1
@dirrm lib/ivl