123 lines
4.4 KiB
C
123 lines
4.4 KiB
C
$NetBSD: patch-src_r600__exa.c,v 1.1 2014/10/26 10:20:42 wiz Exp $
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--- src/r600_exa.c.orig 2012-06-25 08:19:41.000000000 +0000
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+++ src/r600_exa.c
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@@ -246,7 +246,8 @@ R600PrepareSolid(PixmapPtr pPix, int alu
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cb_conf.base = accel_state->dst_obj.offset;
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cb_conf.bo = accel_state->dst_obj.bo;
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#ifdef XF86DRM_MODE
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- cb_conf.surface = accel_state->dst_obj.surface;
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+ if (info->cs)
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+ cb_conf.surface = accel_state->dst_obj.surface;
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#endif
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if (accel_state->dst_obj.bpp == 8) {
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@@ -428,7 +429,8 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
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tex_res.bo = accel_state->src_obj[0].bo;
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tex_res.mip_bo = accel_state->src_obj[0].bo;
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#ifdef XF86DRM_MODE
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- tex_res.surface = accel_state->src_obj[0].surface;
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+ if (info->cs)
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+ tex_res.surface = accel_state->src_obj[0].surface;
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#endif
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if (accel_state->src_obj[0].bpp == 8) {
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tex_res.format = FMT_8;
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@@ -475,7 +477,8 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
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cb_conf.base = accel_state->dst_obj.offset;
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cb_conf.bo = accel_state->dst_obj.bo;
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#ifdef XF86DRM_MODE
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- cb_conf.surface = accel_state->dst_obj.surface;
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+ if (info->cs)
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+ cb_conf.surface = accel_state->dst_obj.surface;
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#endif
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if (accel_state->dst_obj.bpp == 8) {
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cb_conf.format = COLOR_8;
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@@ -626,15 +629,10 @@ R600PrepareCopy(PixmapPtr pSrc, Pixmap
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if (accel_state->same_surface == TRUE) {
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#if defined(XF86DRM_MODE)
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- unsigned long size = accel_state->dst_obj.surface->bo_size;
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- unsigned long align = accel_state->dst_obj.surface->bo_alignment;
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-#else
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- unsigned height = pDst->drawable.height;
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- unsigned long size = height * accel_state->dst_obj.pitch * pDst->drawable.bitsPerPixel/8;
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-#endif
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-
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-#if defined(XF86DRM_MODE)
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if (info->cs) {
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+ unsigned long size = accel_state->dst_obj.surface->bo_size;
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+ unsigned long align = accel_state->dst_obj.surface->bo_alignment;
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+
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if (accel_state->copy_area_bo) {
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radeon_bo_unref(accel_state->copy_area_bo);
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accel_state->copy_area_bo = NULL;
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@@ -656,6 +654,9 @@ R600PrepareCopy(PixmapPtr pSrc, Pixmap
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} else
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#endif
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{
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+ unsigned height = pDst->drawable.height;
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+ unsigned long size = height * accel_state->dst_obj.pitch * pDst->drawable.bitsPerPixel/8;
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+
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if (accel_state->copy_area) {
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exaOffscreenFree(pDst->drawable.pScreen, accel_state->copy_area);
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accel_state->copy_area = NULL;
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@@ -978,7 +979,8 @@ static Bool R600TextureSetup(PicturePtr
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tex_res.bo = accel_state->src_obj[unit].bo;
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tex_res.mip_bo = accel_state->src_obj[unit].bo;
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#ifdef XF86DRM_MODE
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- tex_res.surface = accel_state->src_obj[unit].surface;
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+ if (info->cs)
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+ tex_res.surface = accel_state->src_obj[unit].surface;
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#endif
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tex_res.request_size = 1;
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@@ -1447,7 +1449,8 @@ static Bool R600PrepareComposite(int op,
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cb_conf.format = dst_format;
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cb_conf.bo = accel_state->dst_obj.bo;
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#ifdef XF86DRM_MODE
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- cb_conf.surface = accel_state->dst_obj.surface;
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+ if (info->cs)
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+ cb_conf.surface = accel_state->dst_obj.surface;
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#endif
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switch (pDstPicture->format) {
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@@ -1899,9 +1902,7 @@ R600UploadToScreenCS(PixmapPtr pDst, int
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src_obj.domain = RADEON_GEM_DOMAIN_GTT;
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src_obj.bo = scratch;
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src_obj.tiling_flags = 0;
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-#ifdef XF86DRM_MODE
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src_obj.surface = NULL;
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-#endif
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dst_obj.pitch = dst_pitch_hw;
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dst_obj.width = pDst->drawable.width;
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@@ -1911,9 +1912,7 @@ R600UploadToScreenCS(PixmapPtr pDst, int
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dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
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dst_obj.bo = radeon_get_pixmap_bo(pDst);
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dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
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-#ifdef XF86DRM_MODE
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dst_obj.surface = radeon_get_pixmap_surface(pDst);
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-#endif
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if (!R600SetAccelState(pScrn,
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&src_obj,
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@@ -2040,9 +2039,7 @@ R600DownloadFromScreenCS(PixmapPtr pSrc,
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src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
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src_obj.bo = radeon_get_pixmap_bo(pSrc);
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src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
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-#ifdef XF86DRM_MODE
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src_obj.surface = radeon_get_pixmap_surface(pSrc);
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-#endif
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dst_obj.pitch = scratch_pitch;
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dst_obj.width = w;
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@@ -2052,9 +2049,7 @@ R600DownloadFromScreenCS(PixmapPtr pSrc,
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dst_obj.bpp = bpp;
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dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
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dst_obj.tiling_flags = 0;
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-#ifdef XF86DRM_MODE
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dst_obj.surface = NULL;
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-#endif
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if (!R600SetAccelState(pScrn,
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&src_obj,
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