1a5b0eb1d8
Changelog: * Verilator 4.016 2016-06-16 *** Add --quiet-exit, bug1436. [Todd Strader] **** Error continuation lines no longer have %Error prefix. **** Support logical equivalence operator <->. **** Support VerilatedFstC set_time_unit, bug1433. [Pieter Kapsenberg] **** Support deferred assertions, bug1449. [Charles Eddleston] **** Mark infrequently called functions with GCC cold attribute. **** Fix sign-compare warning in verilated.cpp, bug1437. [Sergey Kvachonok] **** Fix fault on $realtime with %t, bug1443. [Julien Margetts] **** Fix $display with string without %s, bug1441. [Denis Rystsov] **** Fix parameter function string returns, bug1441. [Denis Rystsov] **** Fix invalid XML output due to special chars, bug1444. [Kanad Kanhere] **** Fix performance when mulithreaded on 1 CPU, bug1455. [Stefan Wallentowitz] **** Fix type and real parameter issues, bug1427, bug1456, bug1458. [Todd Strader] **** Fix build error on MinGW, bug1460. [Richard Myers] **** Fix not reporting some duplicate signals, bug1462. [Peter Gerst] **** Fix --savable invalid C++ on packed arrays, bug1465. [Alex Chadwick] **** Fix constant function return of function var, bug1467. [Roman Popov] * Verilator 4.014 2019-05-08 *** Add --trace-fst-thread. **** Support '#' comments in $readmem, bug1411. [Frederick Requin] **** Support "'dx" constants, bug1423. [Udi Finkelstein] **** For FST tracing use LZ4 compression. [Tony Bybell] **** Add error when use parameters without value, bug1424. [Peter Gerst] **** Auto-extend and WIDTH warn on unsized X/Zs, bug1423. [Udi Finkelstein] **** Fix missing VL_SHIFTL_ errors, bug1412, bug1415. [Larry Lee] **** Fix MinGW GCC 6 printf formats, bug1413. [Sergey Kvachonok] **** Fix test problems when missing fst2vcd, bug1417. [Todd Strader] **** Fix GTKWave register warning, bug1421. [Pieter Kapsenberg] **** Fix FST enums not displaying, bug1426. [Danilo Ramos] **** Fix table compile error with multiinterfaces, bug1431. [Bogdan Vukobratovic]
32 lines
788 B
Makefile
32 lines
788 B
Makefile
# $NetBSD: Makefile,v 1.4 2019/08/23 13:05:49 ryoon Exp $
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DISTNAME= verilator-4.016
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CATEGORIES= cad
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MASTER_SITES= https://www.veripool.org/ftp/
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EXTRACT_SUFX= .tgz
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MAINTAINER= ryoon@NetBSD.org
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HOMEPAGE= https://www.veripool.org/wiki/verilator
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COMMENT= Verilog HDL simulator
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LICENSE= gnu-lgpl-v3 OR artistic-2.0
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GNU_CONFIGURE= yes
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FLEX_REQD= 2.6.4
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USE_TOOLS+= bison flex gmake perl pkg-config
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USE_LANGUAGES= c c++
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TOOLS_PLATFORM.flex= # Use flex from pkgsrc
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REPLACE_PERL+= test_regress/*.pl
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REPLACE_PERL+= test_regress/t/*.pl
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CONFIGURE_ENV+= ac_cv_path_YACC=bison
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# for long tests
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TEST_DEPENDS+= p5-Unix-Processors-[0-9]*:../../sysutils/p5-Unix-Processors
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CONFIGURE_ARGS+= --enable-longtests
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TEST_TARGET= test
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PKGCONFIG_OVERRIDE+= verilator.pc.in
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.include "../../mk/bsd.pkg.mk"
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