pkgsrc/cad/verilog-current
dmcmahill 3be1024b8f update to verilog-current-20011020.
changes since last snapshot include:

- addition of a fpga target for synthesis.  outputs edif, optimized for
  xilinx virtex parts.
- fixed bug with synthesis of !=
- fixed bug in hex constant parsing
- fixed vvp bug with subtracting very wide words
- much improved VCD output
- many other bug fixes and robustness improvements.
2001-10-24 12:27:11 +00:00
..
patches update to 20010630 snapshot. 2001-07-03 18:23:46 +00:00
pkg update to verilog-current-20011020. 2001-10-24 12:27:11 +00:00
distinfo update to verilog-current-20011020. 2001-10-24 12:27:11 +00:00
Makefile update to verilog-current-20011020. 2001-10-24 12:27:11 +00:00