aaf127f232
the authors announcement are: There are a few bugs in the main compiler that are fixed. There has also been an extension to the $fopen that adds support for opening files for reading. The $fgetc has been added to take advantage of this. This was done on the VPI side, although a slight extension to the mcd functions was created. The real news is the vvp simulation engine. I've added the tgt-vvp code generator source and the vvp assembler/simulator, and the combination actually produces the occasional working program. And it makes them very quickly. So far as I can tell now, I am going to be very pleased with the final outcome when this work is complete. However, it is not at all ready to use. This snapshot is mostly to give a preview of things to come to a wider audience. HOW VVP WORKS If you are accustomed to the existing vvm behavior, you remember that the vvm simulator works by generating C++ and feeding that to the g++ compiler. Many of you are painfully aware of that. VVP does *not* work like that. Instead of generating C++, the generator emits assembly language for an abstract simulator processor. The processor that the assembly targets doesn't really exist, but the vvp program, included in this Icarus Verilog snapshot, assembles the code to data structures in memory, then efficiently emulates the abstract processor. So the simulation of a program via vvp works by first compiling the Verilog to vvp assembly. The vvp.tgt modules generates the code, and is envoked when you use the ``-tvvp'' switch to iverilog. The vvp assembly file so created is then passed to the vvp program to be assembled and executed. There is a single vvp input file that is the design to simulate. The vvp assembler is designed to execute the design efficiently. HOW TO LEARN MORE The ivl_target.h header file describes the loadable target API that the vvp code generator uses to gain access to the design. Then the tgt-vvp directory contains the implementation of the vvp code generator. The vvp directory contains the implementation of the assembler/simulator that runs the compiled design. The README.txt file describes how the vvp program works in general, and points to other txt files. There are a variety of other .txt files in the vvp directory that describe how the major components of the vvp program work.
24 lines
702 B
Makefile
24 lines
702 B
Makefile
# $NetBSD: Makefile,v 1.14 2001/03/31 00:00:35 dmcmahill Exp $
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#
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DISTNAME= verilog-20010324
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PKGNAME= verilog-current-20010324
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CATEGORIES= cad
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MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
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MAINTAINER= dmcmahill@netbsd.org
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HOMEPAGE= http://icarus.com/eda/verilog/index.html
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COMMENT= Verilog simulation and synthesis tool (development snapshot version)
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BUILD_DEPENDS+= bison-*:../../devel/bison
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BUILD_DEPENDS+= gperf-2.7.2:../../devel/gperf
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DEPENDS+= ipal-current>=20001210:../../cad/ipal-current
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CONFLICTS+= verilog
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GNU_CONFIGURE= yes
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USE_GMAKE= yes
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CPPFLAGS+= -I${LOCALBASE}/include
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CONFIGURE_ENV+= CPPFLAGS="${CPPFLAGS}" LDFLAGS+="${LDFLAGS}"
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.include "../../mk/bsd.pkg.mk"
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