pkgsrc/cad/Makefile
2017-02-21 20:37:03 +00:00

75 lines
1.3 KiB
Makefile

# $NetBSD: Makefile,v 1.94 2017/02/21 20:37:03 plunky Exp $
#
COMMENT= CAD tools
SUBDIR+= MyHDL-gplcver
SUBDIR+= MyHDL-iverilog
SUBDIR+= adms
SUBDIR+= atlc
SUBDIR+= boolean
SUBDIR+= cascade
SUBDIR+= cgi-wcalc
SUBDIR+= covered
SUBDIR+= dinotrace
SUBDIR+= dinotrace-mode
SUBDIR+= diylc
SUBDIR+= eagle
SUBDIR+= electric
SUBDIR+= fastcap
SUBDIR+= fasthenry
SUBDIR+= felt
SUBDIR+= freehdl
SUBDIR+= gdsreader
SUBDIR+= geda
SUBDIR+= gerbv
SUBDIR+= ghdl
SUBDIR+= gnetman
SUBDIR+= gnucap
SUBDIR+= gplcver
SUBDIR+= gsmc
SUBDIR+= gtk1-wcalc
SUBDIR+= gtk2-wcalc
SUBDIR+= gtkwave
SUBDIR+= iverilog
SUBDIR+= kicad
SUBDIR+= kicad-doc
SUBDIR+= kicad-footprints
SUBDIR+= kicad-i18n
SUBDIR+= kicad-lib
SUBDIR+= klayout
SUBDIR+= librecad
SUBDIR+= libwcalc
SUBDIR+= magic
SUBDIR+= mcalc
SUBDIR+= mex-wcalc
SUBDIR+= mpac
SUBDIR+= nelma
SUBDIR+= ng-spice
SUBDIR+= ntesla
SUBDIR+= oce
SUBDIR+= openscad
SUBDIR+= p5-gds2
SUBDIR+= pcb
SUBDIR+= py-MyHDL
SUBDIR+= py-gds
SUBDIR+= py-simpy
SUBDIR+= qcad
SUBDIR+= qcad-partlibrary
SUBDIR+= sci-wcalc
SUBDIR+= solvespace
SUBDIR+= spice
SUBDIR+= spiceprm
SUBDIR+= stdio-wcalc
SUBDIR+= tkgate
SUBDIR+= tnt-mmtl
SUBDIR+= transcalc
SUBDIR+= verilog-mode
SUBDIR+= veriwell
SUBDIR+= vipec
SUBDIR+= wcalc
SUBDIR+= wcalc-docs
SUBDIR+= xchiplogo
SUBDIR+= xcircuit
.include "../mk/misc/category.mk"