4565c457e6
There is no usable changelog; I've found one real bug closed in the tracker: A verilog '>>>' is generated as appropriate for signed numbers.
20 lines
543 B
Makefile
20 lines
543 B
Makefile
# $NetBSD: Makefile,v 1.3 2006/05/04 16:58:05 drochner Exp $
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#
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DISTNAME= myhdl-0.5.1
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PKGNAME= MyHDL-iverilog-0.5.1
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CATEGORIES= cad python
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MASTER_SITES= ${MASTER_SITE_SOURCEFORGE:=myhdl/}
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MAINTAINER= pkgsrc-users@NetBSD.org
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HOMEPAGE= http://jandecaluwe.com/Tools/MyHDL/Overview.html
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COMMENT= Icarus Verilog cosimulation support for py-MyHDL
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BUILD_DIRS+= cosimulation/icarus
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do-install:
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${INSTALL_DATA} ${WRKSRC}/cosimulation/icarus/myhdl.vpi \
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${PREFIX}/lib/ivl
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.include "../../cad/verilog/buildlink3.mk"
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.include "../../mk/bsd.pkg.mk"
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