drochner 4565c457e6 update MyHDL to 0.5.1 ... There is no usable changelog; I've found one real bug closed in the tracker: A verilog '>>>' is generated as appropriate for signed numbers.		2006-05-04 16:58:05 +00:00
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patches	update MyHDL to 0.5.1	2006-05-04 16:58:05 +00:00
DESCR	import MyHDL-gplcver-0.5, a GPL Cver vpi module to support cosimulation	2006-02-10 16:40:02 +00:00
distinfo	update MyHDL to 0.5.1	2006-05-04 16:58:05 +00:00
Makefile	update MyHDL to 0.5.1	2006-05-04 16:58:05 +00:00
PLIST	import MyHDL-gplcver-0.5, a GPL Cver vpi module to support cosimulation	2006-02-10 16:40:02 +00:00