19 lines
848 B
Text
19 lines
848 B
Text
This is SWARM - SoftWare ARM.
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The initial stage in this process is implement a plain software model
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of the basic ARM. There are, of course, already software models of
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the ARM available, so why do another one? Well, this one will need to
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allow the instruction set to be modified at run time, and provide not
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just an execution environment, but also a way of monitoring things
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like cache hits.
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To this end a hierarchical model of an ARM CPU has been implemented in
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C++. It currently supports:
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+ Arm 6 based core. Currently able to handle data processing
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instructions, word/byte load and stores, load/store multiple,
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branches, 32 bit multiplication, and SWIs.
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+ Support for plugging in different caches - be they unified or
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separate I & D caches. Currently only a direct mapped cache is
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implemented.
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+ Compile for SWARM using ARM targeted gcc.
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