70bebbcb5f
synthesis code and bug fixes in the simulation code since the last packaged snapshot.
35 lines
982 B
Makefile
35 lines
982 B
Makefile
# $NetBSD: Makefile,v 1.29 2002/10/13 23:01:27 dmcmahill Exp $
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#
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DISTNAME= verilog-${SNAPDATE}
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PKGNAME= verilog-current-${SNAPDATE}
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CATEGORIES= cad
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MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
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MAINTAINER= dmcmahill@netbsd.org
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HOMEPAGE= http://icarus.com/eda/verilog/index.html
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COMMENT= Verilog simulation and synthesis tool (development snapshot version)
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BUILD_DEPENDS+= bison-[0-9]*:../../devel/bison
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BUILD_DEPENDS+= gperf-2.7.2:../../devel/gperf
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# turn this back on when ipal comes along a little further
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#DEPENDS+= ipal-current>=20001210:../../cad/ipal-current
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CONFLICTS+= verilog-[0-9]*
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SNAPDATE= 20020921
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GNU_CONFIGURE= yes
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USE_GMAKE= yes
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#
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# for ipal.h
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#CPPFLAGS+= -I${LOCALBASE}/include
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#CONFIGURE_ENV+= CPPFLAGS="${CPPFLAGS}" LDFLAGS+="${LDFLAGS}"
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CONFIGURE_ARGS+= --without-ipal
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YACC= ${LOCALBASE}/bin/bison
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test: build
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cd ${WRKSRC} && \
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${MAKE_ENV} ${MAKE_PROGRAM} check 2>&1 | \
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tee ${WRKDIR}/tests.log
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.include "../../mk/bsd.pkg.mk"
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