198b016345
It's a rename of cad/verilog to a better name. Updated DESCR for new package: Icarus Verilog is intended to compile ALL of the Verilog HDL as described in the IEEE-1364 standard. Of course, it's not quite there yet. It does currently handle a mix of structural and behavioral constructs. Icarus Verilog is not aimed at being a simulator in the traditional sense, but a compiler that generates code employed by back-end tools. No objections to rename from <gdt>
6 lines
349 B
Text
6 lines
349 B
Text
Icarus Verilog is intended to compile ALL of the Verilog HDL as described in
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the IEEE-1364 standard. Of course, it's not quite there yet. It does currently
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handle a mix of structural and behavioral constructs.
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Icarus Verilog is not aimed at being a simulator in the traditional sense, but
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a compiler that generates code employed by back-end tools.
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