pkgsrc/cad/py-MyHDL/distinfo
drochner 154f18aa7d update to 0.4.1
changes:
* VCD output for waveform viewing
- function additions
- needs Python 2.3, 2.4 is OK
* Conversion to Verilog to provide a path to implementation
* Added cosimulation support for the cver Verilog simulator.
- bugfixes
2005-01-05 15:20:10 +00:00

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$NetBSD: distinfo,v 1.2 2005/01/05 15:20:10 drochner Exp $
SHA1 (myhdl-0.4.1.tar.gz) = 84096c83351152b1354a331a0b8c3c1bf4098dde
Size (myhdl-0.4.1.tar.gz) = 1205572 bytes