dmcmahill 51cc1f3f79 update to verilog-0.6 ... WHAT'S NEW SINCE 0.5? Quite a lot. Innumerable bugs have been fixed, and standards coverage has been improved significantly. Warning and error messages have been improved, and so has compile performance. Gate delays, strength modeling, and floating point delays have all improved since the 0.5 release. If you had trouble with the 0.5 release, the 0.6 release probably fixes your problem. Support for large designs spanning multiple files has been improved dramatically. The usual preprocessor inclusion method still works, but The 0.6 release adds command files for keeping source file lists, and automatic library searches for missing modules. The library mechinisms are compatible with commercial tools, and commercial module libraries can be used with Icarus Verilog. Many compiler limitations related to the size and complexity of large designs have been relaxed or eliminated. There are no known design size limitations remaining in the compiler. Icarus Verilog should be able to handle any design that you have the patience to compile.		2002-02-08 01:48:31 +00:00
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patches	update to verilog-0.5	2001-08-04 01:20:43 +00:00
DESCR	Move pkg/ files into package's toplevel directory	2001-11-01 00:47:39 +00:00
distinfo	update to verilog-0.6	2002-02-08 01:48:31 +00:00
Makefile	update to verilog-0.6	2002-02-08 01:48:31 +00:00
PLIST	update to verilog-0.6	2002-02-08 01:48:31 +00:00