8c86f20066
* flex from NetBSD base causes build failure, so use pkgsrc/devel/flex instead.
Changelog:
* Verilator 4.012 2019-3-23
*** Add +verilator+seed, bug1396. [Stan Sokorac]
*** Support $fread. [Leendert van Doorn]
*** Support void' cast on functions called as tasks, bug1383. [Al Grant]
*** Add IGNOREDRETURN warning, bug1383.
**** Report PORTSHORT errors on concat constants, bug 1400. [Will Korteland]
**** Fix VERILATOR_GDB being ignored, msg2860. [Yu Sheng Lin]
**** Fix $value$plus$args missing verilated_heavy.h. [Yi-Chung Chen]
**** Fix MSVC compile error, bug1406. [Benjamin Gartner]
**** Fix maintainer test when no Parallel::Forker, msg2630. [Enzo Chi]
**** Fix +1364-1995ext flags applying too late, bug1384. [Al Grant]
* Verilator 4.010 2019-01-27
*** Removed --trace-lxt2, use --trace-fst instead.
**** For --xml, add additional information, bug1372. [Jonathan Kimmitt]
**** Add circular typedef error, bug1388. [Al Grant]
**** Add unsupported for loops error, msg2692. [Yu Sheng Lin]
**** Fix FST tracing of wide arrays, bug1376. [Aleksander Osman]
**** Fix error when pattern assignment has too few elements, bug1378. [Viktor Tomov]
**** Fix error when no modules in $unit, bug1381. [Al Grant]
**** Fix missing too many digits warning, bug1380. [Jonathan Kimmitt]
**** Fix uninitialized data in verFiles and unroller, bug1385. bug1386. [Al Grant]
**** Fix internal error on xrefs into unrolled functions, bug1387. [Al Grant]
**** Fix DPI export void compiler error, bug1391. [Stan Sokorac]
* Verilator 4.008 2018-12-01
*** Support "ref" and "const ref" pins and functions, bug1360. [Jake Longo]
*** In --xml-only show the original unmodified names, and add module_files
and cells similar to Verilog-Perl, msg2719. [Kanad Kanhere]
**** Add CONTASSREG error on continuous assignments to regs, bug1369. [Peter Gerst]
**** Add PROCASSWIRE error on behavioral assignments to wires, msg2737. [Neil Turton]
**** Add IMPORTSTAR warning on import::* inside $unit scope.
**** Fix --trace-lxt2 compile error on MinGW, msg2711. [HyungKi Jeong]
**** Fix hang on bad pattern keys, bug1364. [Matt Myers]
**** Fix crash due to cygwin bug in getline, bug1349. [Affe Mao]
**** Fix __Slow files getting compiled with OPT_FAST, bug1370. [Thomas Watts]
32 lines
788 B
Makefile
32 lines
788 B
Makefile
# $NetBSD: Makefile,v 1.2 2019/04/01 12:22:53 ryoon Exp $
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DISTNAME= verilator-4.012
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CATEGORIES= cad
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MASTER_SITES= https://www.veripool.org/ftp/
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EXTRACT_SUFX= .tgz
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MAINTAINER= ryoon@NetBSD.org
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HOMEPAGE= https://www.veripool.org/wiki/verilator
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COMMENT= Verilog HDL simulator
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LICENSE= gnu-lgpl-v3 OR artistic-2.0
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GNU_CONFIGURE= yes
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FLEX_REQD= 2.6.4
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USE_TOOLS+= bison flex gmake perl pkg-config
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USE_LANGUAGES= c c++
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TOOLS_PLATFORM.flex= # Use flex from pkgsrc
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REPLACE_PERL+= test_regress/*.pl
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REPLACE_PERL+= test_regress/t/*.pl
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CONFIGURE_ENV+= ac_cv_path_YACC=bison
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# for long tests
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TEST_DEPENDS+= p5-Unix-Processors-[0-9]*:../../sysutils/p5-Unix-Processors
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CONFIGURE_ARGS+= --enable-longtests
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TEST_TARGET= test
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PKGCONFIG_OVERRIDE+= verilator.pc.in
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.include "../../mk/bsd.pkg.mk"
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