9c45065ef2
Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test. Typically in the design verification work flow, a design verification engineer will develop a self-checking test suite to verify design elements/functions specified by a design's specification document. When the test suite contains all of the tests required by the design specification, the test writer may be asking him/herself, "How much logic in the design is actually being exercised?", "Does my test suite cover all of the logic under test?", and "Am I done writing tests for the logic?". When the design verification gets to this point, it is often useful to get some metrics for determining logic coverage. This is where a code coverage utility, such as Covered, is very useful. Please note that this package is for a stable release version. There is a seperate package (covered-current) which is made of development snapshots.
28 lines
718 B
Makefile
28 lines
718 B
Makefile
# $NetBSD: Makefile,v 1.1.1.1 2003/08/24 18:38:06 dmcmahill Exp $
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#
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DISTNAME= covered-0.2.1
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CATEGORIES= cad
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MASTER_SITES= ${MASTER_SITE_SOURCEFORGE:=covered/}
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MAINTAINER= dmcmahill@NetBSD.org
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HOMEPAGE= http://covered.sourceforge.net/
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COMMENT= Verilog code coverage analyzer (stable release version)
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BUILD_DEPENDS+= bison-[0-9]*:../../devel/bison
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BUILD_DEPENDS+= gperf-2.7.2:../../devel/gperf
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DEPENDS+= verilog{,-current}-[0-9]*:../../cad/verilog
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CONFLICTS+= covered-current-[0-9]*
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USE_PERL5= YES
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REPLACE_PERL= ${WRKSRC}/diags/verilog/check_test
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GNU_CONFIGURE= YES
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USE_GMAKE= YES
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TEST_DIRS= ${WRKSRC}/diags/regress
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TEST_TARGET= #defined
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post-patch:
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${CHMOD} 755 ${WRKSRC}/missing
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.include "../../mk/bsd.pkg.mk"
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