2ce70215a8
Not very many overall changes. Main ones include
1. Support for powerpc, arm32 and vax
2. Makefile.gcc can now be included by anything which depends on gcc versions.
If the version installed isn't 2.95.3 it'll add itself as a BUILD_DEPENDS.
(XXX: any of the makefile's in pkgsrc should be checked and change to use
this)
3. Remove special PLIST.NetBSD-sparc as it's no longer needed
4. Change post-extract loop to pick up any arch files from FILESDIR without
having to hardcode all the archs
5. Remove arch restrictions as this should work on any arch supported by the
main source tree as of 03/28/02
6. Add PKGREVISION as this clearly isn't stock 2.95.3 (it doesn't change
gcc --version so version checks won't care).
114 lines
3.3 KiB
Text
114 lines
3.3 KiB
Text
$NetBSD: patch-af,v 1.4 2002/03/28 10:11:52 jmc Exp $
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--- ../gcc-2.95.3/gcc/config/arm/arm.c.orig 2001/04/23 11:59:30 1.1.1.2
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+++ ../gcc-2.95.3/gcc/config/arm/arm.c 2001/12/19 23:14:50 1.4
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@@ -281,7 +281,7 @@
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if (ptr->string != NULL && ptr->string[0] != '\0')
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{
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- struct processors * sel;
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+ const struct processors * sel;
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for (sel = ptr->processors; sel->name != NULL; sel ++)
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if (streq (ptr->string, sel->name))
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@@ -566,7 +566,7 @@
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if (!reload_completed
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|| current_function_pretend_args_size
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|| current_function_anonymous_args
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- || ((get_frame_size () + current_function_outgoing_args_size != 0)
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+ || ((arm_get_frame_size () + current_function_outgoing_args_size != 0)
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&& !(TARGET_APCS && frame_pointer_needed)))
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return 0;
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@@ -5397,6 +5397,18 @@
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return "";
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}
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+/* Generate a sequence of insns that will generate the correct return
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+ address mask depending on the physical architecture that the program
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+ is running on. */
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+rtx
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+arm_gen_return_addr_mask ()
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+{
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+ rtx reg = gen_reg_rtx (Pmode);
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+
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+ emit_insn (gen_return_addr_mask (reg));
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+ return reg;
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+}
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+
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/* Return nonzero if optimizing and the current function is volatile.
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Such functions never return, and many memory cycles can be saved
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by not storing register values that will never be needed again.
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@@ -5828,11 +5840,71 @@
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emit_insn (par);
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}
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+/* Calculate the size of the stack frame, taking into account any
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+ padding that is required to ensure stack-alignment. */
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+int arm_get_frame_size ()
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+{
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+ int regno;
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+
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+ int base_size = (get_frame_size () + 3) & ~3;
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+ int entry_size = 0;
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+ int live_regs_mask = 0;
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+ int volatile_func = (optimize > 0
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+ && TREE_THIS_VOLATILE (current_function_decl));
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+
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+ if (! TARGET_ATPCS_STACK_ALIGN)
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+ return base_size;
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+
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+ /* We know that SP will be word aligned on entry, and we must
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+ preserve that condition at any subroutine call. But those are
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+ the only constraints. */
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+
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+ /* Space for variadic functions. */
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+ if (current_function_pretend_args_size)
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+ entry_size += current_function_pretend_args_size;
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+
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+ if (! volatile_func)
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+ {
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+ for (regno = 0; regno <= 10; regno++)
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+ if (regs_ever_live[regno] && ! call_used_regs[regno])
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+ live_regs_mask |= 1 << regno;
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+
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+ if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
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+ live_regs_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
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+
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+ if (regs_ever_live[14])
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+ live_regs_mask |= 0x4000;
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+ }
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+
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+ if (frame_pointer_needed)
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+ live_regs_mask |= 0xD800;
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+
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+ /* If we have to push any registers, we must also push lr as well. */
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+ if (live_regs_mask)
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+ live_regs_mask |= 0x4000;
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+
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+ for (regno = 0; regno < 16; regno++)
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+ if (live_regs_mask & (1 << regno))
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+ entry_size += 4;
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+
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+ if (! volatile_func)
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+ {
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+ for (regno = 23; regno > 15; regno--)
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+ if (regs_ever_live[regno] && ! call_used_regs[regno])
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+ entry_size += 12;
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+ }
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+
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+ if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
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+ base_size += 4;
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+
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+ return base_size;
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+}
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+
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void
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arm_expand_prologue ()
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{
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int reg;
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- rtx amount = GEN_INT (-(get_frame_size ()
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+ rtx amount = GEN_INT (-(arm_get_frame_size ()
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+ current_function_outgoing_args_size));
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int live_regs_mask = 0;
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int store_arg_regs = 0;
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