16 lines
966 B
Text
16 lines
966 B
Text
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
|
|
compiler, compiling source code writen in Verilog (IEEE-1364) into some target
|
|
format. For batch simulation, the compiler can generate C++ code that is
|
|
compiled and linked with a run time library (called "vvm") then executed as
|
|
a command to run the simulation. For synthesis, the compiler generates
|
|
netlists in the desired format.
|
|
|
|
The compiler proper is intended to parse and elaborate design descriptions
|
|
written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
|
|
complex standard, so it will take some time for it to get there, but that's
|
|
the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
|
|
and some -1999 features will creep in.
|
|
|
|
Please note that this package is a development snapshot and while it contains
|
|
the latest and greatest features, it may be buggy as well. There is a separate
|
|
verilog package which is made of the stable releases.
|