6.0.1:
Non-comprehensive list of changes in this release
Support for retpolines was added to help mitigate “branch target injection” (variant 2) of the “Spectre” speculative side channels described by Project Zero and the Spectre paper.
The Redirects argument of llvm::sys::ExecuteAndWait and llvm::sys::ExecuteNoWait was changed to an ArrayRef of optional StringRef‘s to make it safer and more convenient to use.
The backend name was added to the Target Registry to allow run-time information to be fed back into TableGen. Out-of-tree targets will need to add the name used in the def X : Target definition to the call to RegisterTarget.
The Debugify pass was added to opt to facilitate testing of debug info preservation. This pass attaches synthetic DILocations and DIVariables to the instructions in a Module. The CheckDebugify pass determines how much of the metadata is lost.
Significantly improved quality of CodeView debug info for Windows.
Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer).
Changes to the LLVM IR
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The fast-math-flags (FMF) have been updated. Previously, the ‘fast’ flag indicated that floating-point reassociation was allowed and all other flags were set too. The ‘fast’ flag still exists, but there is a new flag called ‘reassoc’ to indicate specifically that reassociation is allowed. A new bit called ‘afn’ was also added to selectively allow approximations for common mathlib functions like square-root. The new flags provide more flexibility to enable/disable specific floating-point optimizations. Making the optimizer respond appropriately to these flags is an ongoing effort.
Changes to the AArch64 Target
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Enabled the new GlobalISel instruction selection framework by default at -O0.
Changes to the ARM Target
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Support for enabling SjLj exception handling on platforms where it isn’t the default.
Changes to the Hexagon Target
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The Hexagon backend now supports V65 ISA.
The -mhvx option now takes an optional value that specifies the ISA version of the HVX coprocessor. The available values are v60, v62 and v65. By default, the value is set to be the same as the CPU version.
The compiler option -mhvx-double is deprecated and will be removed in the next release of the compiler. Programmers should use the -mhvx-length option to specify the desired vector length: -mhvx-length=64b for 64-byte vectors and -mhvx-length=128b for 128-byte vectors. While the current default vector length is 64 bytes, users should always specify the length explicitly, since the default value may change in the future.
The target feature hvx-double is deprecated and will be removed in the next release. LLVM IR generators should use target features hvx-length64b and hvx-length128b to indicate the vector length. The length should always be specified when HVX code generation is enabled.
Changes to the MIPS Target
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Fixed numerous bugs:
fpowi on MIPS64 giving incorrect results when used with a negative integer.
Usage of the asm ‘c’ constraint with the wrong datatype causing an assert/crash.
Fixed a conversion bug when using the DSP ASE.
Fixed an inconsistency where objects were not marked as using the microMIPS as when the micromips function attribute or the ”.set micromips” directive was used.
Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot filler, fixing a class of rare edge case bugs where the delay slot filler would violate ISA restrictions.
Fixed a crash when using a type of unknown size with gp relative addressing.
Corrected the j macro for microMIPS.
Corrected the encoding of movep for microMIPS32r6.
Fixed an issue with the usage of insert instructions having an invalid set of operands.
Fixed an issue where TLS symbols were not marked as such.
Enabled the usage of register scavenging with MSA, due to its shorter offsets for loads and stores.
Corrected the ELF headers when using the DSP ASE.
New features:
The long branch pass now generates some R6 specific instructions when targeting MIPSR6.
The delay slot filler now performs more branch conversions if delay slots cannot be filled.
The MIPS MT ASE is now fully supported.
Added support for the lapc pseudo instruction.
Improved the selection of multiple instructions (dext, nmadd, nmsub).
Further improved microMIPS codesize reduction.
Deprecation notices:
microMIPS64R6 support was been deprecated since 5.0, and has now been completely removed.
Changes to the SystemZ Target
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During this release the SystemZ target has:
Added support for 128-bit atomic operations.
Added support for the “o” constraint for inline asm statements.
Changes to the X86 Target
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During this release the X86 target has:
Added support for enabling SjLj exception handling on platforms where it isn’t the default.
Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI.
Added support for Intel Icelake CPU.
Fixed some X87 codegen bugs.
Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs.
Improved scheduler model for AMD Jaguar CPUs.
Improved llvm-mc’s disassembler for some EVEX encoded instructions.
Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions.
Improved codegen for memory comparisons
Improved codegen for i32 vector multiplies
Improved codegen for scalar integer absolute values
Improved codegen for vector integer rotations (XOP and AVX512)
Improved codegen of data being transferred between GPRs and K-registers.
Improved codegen for vector truncations.
Improved folding of address computations into gather/scatter instructions.
Gained initial support recognizing variable shuffles from vector element extracts and inserts.
Improved documentation for SSE/AVX intrinsics in intrin.h header files.
Gained support for emitting retpolines, including automatic insertion of the necessary thunks or using external thunks.
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