198b016345
It's a rename of cad/verilog to a better name. Updated DESCR for new package: Icarus Verilog is intended to compile ALL of the Verilog HDL as described in the IEEE-1364 standard. Of course, it's not quite there yet. It does currently handle a mix of structural and behavioral constructs. Icarus Verilog is not aimed at being a simulator in the traditional sense, but a compiler that generates code employed by back-end tools. No objections to rename from <gdt>
58 lines
1.2 KiB
Text
58 lines
1.2 KiB
Text
@comment $NetBSD: PLIST,v 1.1 2016/10/08 23:01:45 kamil Exp $
|
|
bin/iverilog
|
|
bin/iverilog-vpi
|
|
bin/vvp
|
|
include/iverilog/_pli_types.h
|
|
include/iverilog/acc_user.h
|
|
include/iverilog/ivl_target.h
|
|
include/iverilog/sv_vpi_user.h
|
|
include/iverilog/veriuser.h
|
|
include/iverilog/vpi_user.h
|
|
lib/ivl/blif-s.conf
|
|
lib/ivl/blif.conf
|
|
lib/ivl/blif.tgt
|
|
lib/ivl/cadpli.vpl
|
|
lib/ivl/include/constants.vams
|
|
lib/ivl/include/disciplines.vams
|
|
lib/ivl/ivl
|
|
lib/ivl/ivlpp
|
|
lib/ivl/null-s.conf
|
|
lib/ivl/null.conf
|
|
lib/ivl/null.tgt
|
|
lib/ivl/pcb-s.conf
|
|
lib/ivl/pcb.conf
|
|
lib/ivl/pcb.tgt
|
|
lib/ivl/sizer-s.conf
|
|
lib/ivl/sizer.conf
|
|
lib/ivl/sizer.tgt
|
|
lib/ivl/stub-s.conf
|
|
lib/ivl/stub.conf
|
|
lib/ivl/stub.tgt
|
|
lib/ivl/system.sft
|
|
lib/ivl/system.vpi
|
|
lib/ivl/v2005_math.sft
|
|
lib/ivl/v2005_math.vpi
|
|
lib/ivl/v2009.sft
|
|
lib/ivl/v2009.vpi
|
|
lib/ivl/va_math.sft
|
|
lib/ivl/va_math.vpi
|
|
lib/ivl/vhdl-s.conf
|
|
lib/ivl/vhdl.conf
|
|
lib/ivl/vhdl.tgt
|
|
lib/ivl/vhdl_sys.sft
|
|
lib/ivl/vhdl_sys.vpi
|
|
lib/ivl/vhdlpp
|
|
lib/ivl/vlog95-s.conf
|
|
lib/ivl/vlog95.conf
|
|
lib/ivl/vlog95.tgt
|
|
lib/ivl/vpi_debug.vpi
|
|
lib/ivl/vvp-s.conf
|
|
lib/ivl/vvp.conf
|
|
lib/ivl/vvp.tgt
|
|
lib/libveriuser.a
|
|
lib/libvpi.a
|
|
man/man1/iverilog-vpi.1
|
|
man/man1/iverilog.1
|
|
man/man1/vvp.1
|
|
share/doc/ivl/QUICK_START.txt
|
|
share/doc/ivl/README.txt
|