4565c457e6
There is no usable changelog; I've found one real bug closed in the tracker: A verilog '>>>' is generated as appropriate for signed numbers.
78 lines
2.6 KiB
Text
78 lines
2.6 KiB
Text
@comment $NetBSD: PLIST,v 1.5 2006/05/04 16:58:05 drochner Exp $
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${PYSITELIB}/myhdl/_Cosimulation.py
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${PYSITELIB}/myhdl/_Cosimulation.pyc
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${PYSITELIB}/myhdl/_Cosimulation.pyo
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${PYSITELIB}/myhdl/_Signal.py
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${PYSITELIB}/myhdl/_Signal.pyc
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${PYSITELIB}/myhdl/_Signal.pyo
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${PYSITELIB}/myhdl/_Simulation.py
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${PYSITELIB}/myhdl/_Simulation.pyc
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${PYSITELIB}/myhdl/_Simulation.pyo
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${PYSITELIB}/myhdl/_Waiter.py
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${PYSITELIB}/myhdl/_Waiter.pyc
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${PYSITELIB}/myhdl/_Waiter.pyo
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${PYSITELIB}/myhdl/__init__.py
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${PYSITELIB}/myhdl/__init__.pyc
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${PYSITELIB}/myhdl/__init__.pyo
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${PYSITELIB}/myhdl/_always.py
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${PYSITELIB}/myhdl/_always.pyc
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${PYSITELIB}/myhdl/_always.pyo
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${PYSITELIB}/myhdl/_always_comb.py
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${PYSITELIB}/myhdl/_always_comb.pyc
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${PYSITELIB}/myhdl/_always_comb.pyo
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${PYSITELIB}/myhdl/_bin.py
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${PYSITELIB}/myhdl/_bin.pyc
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${PYSITELIB}/myhdl/_bin.pyo
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${PYSITELIB}/myhdl/_cell_deref.py
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${PYSITELIB}/myhdl/_cell_deref.pyc
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${PYSITELIB}/myhdl/_cell_deref.pyo
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${PYSITELIB}/myhdl/_concat.py
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${PYSITELIB}/myhdl/_concat.pyc
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${PYSITELIB}/myhdl/_concat.pyo
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${PYSITELIB}/myhdl/_delay.py
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${PYSITELIB}/myhdl/_delay.pyc
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${PYSITELIB}/myhdl/_delay.pyo
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${PYSITELIB}/myhdl/_enum.py
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${PYSITELIB}/myhdl/_enum.pyc
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${PYSITELIB}/myhdl/_enum.pyo
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${PYSITELIB}/myhdl/_extractHierarchy.py
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${PYSITELIB}/myhdl/_extractHierarchy.pyc
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${PYSITELIB}/myhdl/_extractHierarchy.pyo
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${PYSITELIB}/myhdl/_instance.py
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${PYSITELIB}/myhdl/_instance.pyc
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${PYSITELIB}/myhdl/_instance.pyo
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${PYSITELIB}/myhdl/_intbv.py
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${PYSITELIB}/myhdl/_intbv.pyc
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${PYSITELIB}/myhdl/_intbv.pyo
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${PYSITELIB}/myhdl/_isGenSeq.py
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${PYSITELIB}/myhdl/_isGenSeq.pyc
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${PYSITELIB}/myhdl/_isGenSeq.pyo
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${PYSITELIB}/myhdl/_join.py
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${PYSITELIB}/myhdl/_join.pyc
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${PYSITELIB}/myhdl/_join.pyo
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${PYSITELIB}/myhdl/_misc.py
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${PYSITELIB}/myhdl/_misc.pyc
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${PYSITELIB}/myhdl/_misc.pyo
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${PYSITELIB}/myhdl/_simulator.py
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${PYSITELIB}/myhdl/_simulator.pyc
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${PYSITELIB}/myhdl/_simulator.pyo
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${PYSITELIB}/myhdl/_toVerilog/__init__.py
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${PYSITELIB}/myhdl/_toVerilog/__init__.pyc
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${PYSITELIB}/myhdl/_toVerilog/__init__.pyo
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${PYSITELIB}/myhdl/_toVerilog/_analyze.py
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${PYSITELIB}/myhdl/_toVerilog/_analyze.pyc
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${PYSITELIB}/myhdl/_toVerilog/_analyze.pyo
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${PYSITELIB}/myhdl/_toVerilog/_convert.py
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${PYSITELIB}/myhdl/_toVerilog/_convert.pyc
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${PYSITELIB}/myhdl/_toVerilog/_convert.pyo
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${PYSITELIB}/myhdl/_traceSignals.py
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${PYSITELIB}/myhdl/_traceSignals.pyc
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${PYSITELIB}/myhdl/_traceSignals.pyo
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${PYSITELIB}/myhdl/_unparse.py
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${PYSITELIB}/myhdl/_unparse.pyc
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${PYSITELIB}/myhdl/_unparse.pyo
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${PYSITELIB}/myhdl/_util.py
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${PYSITELIB}/myhdl/_util.pyc
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${PYSITELIB}/myhdl/_util.pyo
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@dirrm ${PYSITELIB}/myhdl/_toVerilog
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@dirrm ${PYSITELIB}/myhdl
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