5c4c910aca
Release Notes for Icarus Verilog 0.8.7 none (but see below for other releases since the last version in pkgsrc) Release Notes for Icarus Verilog 0.8.6 This is a bug fix update of the 0.8 stable version of Icarus Verilog. The v0.8 series tries to remain as stable as possible while still fixing bugs that are safe to fix. Preprocessor: * Fix parse/preprocess of C-style comments in surpressed ifdef blocks. * Support leading underscore in preprocessor names. Compilation/elaboration issues: * Support min:typ:max expressions in more places. * Fix handling of @* non-input nets. * Do not support system functions in continuous assignments. * Do not support converting vectors to real. * Do not support constant real valued expressions. Run-time ussues: * Fix comparison of negative numbers that happen to be equal. * Fix bad execution of certain expressions caused by code generator bad lookaside handling. * Proper error message for invalid bit selects. * Implement $printtimescale system task. Compiler build issues: * Compile OK evel if libbzip2 is not installed, but do not support LXT2 in that case. Release Notes for Icarus Verilog 0.8.5 This is mostly a bug-fix release for the 0.8 stable branch. * Fix assertions from unary operators with certain operand widths. * Fix incorrect comparison results when in certain cases comparing two signed negative integers. * Latch synthesis has been added to the core synthesizer * Add nand gate support to the edif code generator * Minor compile time errors/warnings * Improved messages from the configure script Release Notes for Icarus Verilog 0.8.4 This is a bug-fix release for the 0.8 stable branch. The 0.8 stable branch updates do not include significant new features (they go into the devel branch instead) nor fixes that are deemed to drastic to include in a stable tool. - Various source code portability problems have been fixed. The 0.8 no longer compiles on many modern systems. - Various bug reports have been put to rest with this release. Some parser errors have been fixed (including a few regressions from 0.8.3) and a few new syntaxes added. - A variety of systhesis bug fixes and enhancements are included in 0.8.4. Currently, synthesis is only actively supported in the 0.8 branch, and the 0.8.4 is the most complete. |
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| .. | ||
| adms | ||
| atlc | ||
| boolean | ||
| cascade | ||
| cgi-wcalc | ||
| covered | ||
| covered-current | ||
| dinotrace | ||
| dinotrace-mode | ||
| eagle | ||
| electric | ||
| fastcap | ||
| fasthenry | ||
| felt | ||
| gattrib | ||
| gdsreader | ||
| geda | ||
| geda-docs | ||
| geda-examples | ||
| geda-symbols | ||
| geda-utils | ||
| gerbv | ||
| gnetlist | ||
| gnetman | ||
| gnucap | ||
| gplcver | ||
| gschem | ||
| gsmc | ||
| gsymcheck | ||
| gtk1-wcalc | ||
| gtk2-wcalc | ||
| gtkwave | ||
| gwave | ||
| lc | ||
| libgeda | ||
| libwcalc | ||
| magic | ||
| mcalc | ||
| mex-wcalc | ||
| mpac | ||
| MyHDL-gplcver | ||
| MyHDL-iverilog | ||
| nelma | ||
| ng-spice | ||
| ntesla | ||
| oct-wcalc | ||
| pcb | ||
| py-MyHDL | ||
| py-simpy | ||
| qcad | ||
| qcad-manual-cs | ||
| qcad-manual-de | ||
| qcad-manual-en | ||
| qcad-manual-hu | ||
| qcad-partlibrary | ||
| sci-wcalc | ||
| simian | ||
| simian-docs | ||
| spice | ||
| spiceprm | ||
| stdio-wcalc | ||
| tkgate | ||
| tnt-mmtl | ||
| transcalc | ||
| verilog | ||
| verilog-current | ||
| verilog-mode | ||
| vipec | ||
| wcalc | ||
| wcalc-docs | ||
| xchiplogo | ||
| xcircuit | ||
| Makefile | ||