46 lines
1.7 KiB
Python
46 lines
1.7 KiB
Python
$NetBSD: patch-myhdl_conversion___toVHDL.py,v 1.1 2018/12/27 16:01:54 joerg Exp $
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--- myhdl/conversion/_toVHDL.py.orig 2018-12-25 21:40:10.283137098 +0000
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+++ myhdl/conversion/_toVHDL.py
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@@ -1838,12 +1838,12 @@ class _ConvertAlwaysSeqVisitor(_ConvertV
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senslist = self.tree.senslist
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edge = senslist[0]
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reset = self.tree.reset
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- async = reset is not None and reset.async
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+ is_async = reset is not None and reset.is_async
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sigregs = self.tree.sigregs
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varregs = self.tree.varregs
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self.write("%s: process (" % self.tree.name)
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self.write(edge.sig)
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- if async:
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+ if is_async:
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self.write(', ')
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self.write(reset)
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self.write(") is")
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@@ -1853,7 +1853,7 @@ class _ConvertAlwaysSeqVisitor(_ConvertV
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self.writeline()
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self.write("begin")
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self.indent()
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- if not async:
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+ if not is_async:
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self.writeline()
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self.write("if %s then" % edge._toVHDL())
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self.indent()
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@@ -1870,7 +1870,7 @@ class _ConvertAlwaysSeqVisitor(_ConvertV
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self.write("%s := %s;" % (n, _convertInitVal(reg, init)))
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self.dedent()
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self.writeline()
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- if async:
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+ if is_async:
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self.write("elsif %s then" % edge._toVHDL())
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else:
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self.write("else")
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@@ -1881,7 +1881,7 @@ class _ConvertAlwaysSeqVisitor(_ConvertV
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self.writeline()
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self.write("end if;")
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self.dedent()
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- if not async:
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+ if not is_async:
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self.writeline()
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self.write("end if;")
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self.dedent()
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