17 lines
989 B
Text
17 lines
989 B
Text
Covered is a Verilog code coverage analysis tool that can be useful
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for determining how well a diagnostic test suite is covering the
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design under test. Typically in the design verification work flow, a
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design verification engineer will develop a self-checking test suite
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to verify design elements/functions specified by a design's
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specification document. When the test suite contains all of the tests
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required by the design specification, the test writer may be asking
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him/herself, "How much logic in the design is actually being
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exercised?", "Does my test suite cover all of the logic under test?",
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and "Am I done writing tests for the logic?". When the design
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verification gets to this point, it is often useful to get some
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metrics for determining logic coverage. This is where a code coverage
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utility, such as Covered, is very useful.
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Please note that this package is for a stable release version.
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There is a separate package (covered-current) which is made of
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development snapshots.
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