9 lines
492 B
Text
9 lines
492 B
Text
MyHDL is a Python package for using Python as a hardware
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description language. Popular hardware description languages, like
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Verilog and VHDL, are compiled languages. MyHDL with Python
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can be viewed as a "scripting language" counterpart of such
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languages. However, Python is more accurately described as a very
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high level language (VHLL). MyHDL users have access to the
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amazing power and elegance of Python for their modeling work.
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This package is GPL Cver cosimulation support for py-MyHDL.
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